The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC. One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands. Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.

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Avec l'arrivée des systèmes radio mobiles de troisième et de quatrième génération, les standards de communications ont tendance à occuper plus de bande pour pouvoir assurer des services de voix, de données et de multimédia. En parallèle, le terminal mobile doit être reconfigurable pour couvrir à la fois le service cellulaire et la connectivité de données. Dans ce contexte, la tendance est d'intégrer les fonctions radio et bandes de base sur le même substrat en utilisant la technologie CMOS afin de réduire la surface, le coût de fabrication et la consommation des terminaux sans fils. Récemment, de nouvelles architectures de réception radio dites " échantillonnées " sont apparues (TexasInstruments, STMicroelectronics, UCLA). Dans ce cas, l'échantillonnage est fait directement sur le signal RF et la majorité du traitement de signal se fait en temps-discret par des capacités commutées. L'évolution de la technologie CMOS et la miniaturisation des transistors rendent la conception analogique de plus en plus difficile (capacités parasites, bruit, linéarité, etc.). De nouveaux effets parasites apparaissent comme la fuite de grille qui inquiète désormais les technologues et les concepteurs de circuits. D'un autre côté, des contraintes de dynamique surgissent avec la diminution des tensions d'alimentation et le bruit des circuits numériques de plus en plus denses augmente considérablement. Le but de ce travail de thèse est de répondre à la question de la portabilité de la solution échantillonnée, en étudiant l'impact des différents effets parasites cités précédemment sur les performances radio de la solution. Ainsi, les critères de portabilité qui sont considérés sont la reconfigurabilité, l'immunité aux effets parasites, l'adaptation à la baisse des tensions d'alimentation, la surface, la consommation et la facilité de conception. Ce travail de thèse a été basé sur des études théoriques et sur des simulations d'une solution échantillonnée de réception radio. Afin d'affronter réellement les problématiques de portabilité, un portage d'une chaîne de réception échantillonnée Wi-Fi/WiMAX de CMOS 65nm à 45nm a été réalisé. Les résultats de mesures obtenus sur ce circuit donnent une grande confiance vis-à-vis des performances radio de la solution échantillonnée et constituent un premier élément de réponse concret à la question de portabilité étudiée.

<p>In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.</p>

In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.