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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Design and implementation of a Radio-Frequency detection algorithm for use within A Radio-Frequency System on Chip

Jereb, Alexander Robert January 2020 (has links)
No description available.
2

Range-Doppler Map Processing Chain For Marine Radar On FPGA Of An RFSoC

Ogilvie, Nickolas W 01 June 2023 (has links) (PDF)
To improve the accuracy and resolution of the measurements, radar systems employ increasingly complex, resource-intensive signal processing, larger bandwidths, and higher carrier frequencies. However, implementing these improvements requires more expensive, complex electronics that are larger and use more power. Using RFSoC (Radio Frequency System on Chips) in radars can address these challenges. By combining processors, an FPGA (Field Programmable Gate Array), and RF data converters into a single integrated circuit, RFSoCs allow for radar electronics that are physically smaller, use less power, and are simpler to design. As using RFSoCs to perform RF data conversion for radars has been already explored, this work focuses on performing radar processing for a marine radar with an RFSoC. Performance specifications for a marine radar are defined based on the specifications for other modern marine radars, a suitable radar waveform is designed based on the derived performance specifications, and a processing chain to compute the range-doppler map is implemented based on the radar specifications and waveform. The processing chain, created as a block design in the Vivado Design Suite, consists of matched filtering and doppler processing. The processing chain is simulated in Vivado and implemented on the FPGA of a Xilinx ZCU216 RFSoC Evaluation Board. To verify the operation of the processing chain, the range-doppler maps generated by simulation and from running the design on the ZCU216 board are compared with range-doppler maps generated by a processing model implemented in MATLAB. The range-doppler map processing chain performs correctly as the outputs from simulation and the ZCU216 show close agreement with the MATLAB results with average percent differences on the order of 10-4 % to 10-5 % and average differences on the order of 10-7. The processing chain generates the range-doppler map quickly: the final range-doppler value is output 1.75 milliseconds after the final sample of a CPI (Coherent Processing Interval) of radar data (the total CPI duration is 10.49 milliseconds) is input. The FPGA resource usage of the processing chain is 85% of the BRAM, 0% of the URAM, 0.87% of the DSP slices, and approximately 1% of the configurable logic blocks. The low resource usage of the processing chain allows for possibilities of future expansion of the processing chain to include radar processing techniques such as digital beamforming or threshold estimation.
3

Digital Microwave Control of Superconducting Qubits / Digital Mikrovågskontroll av Supraledande Kvantbitar

Di Carlo, Giuseppe Ruggero January 2022 (has links)
We manipulate two superconducting qubits using digital microwave electronics. Starting fromtheir characterization, we develop a real-time reset scheme and implement the iSwap gate. Thequbits’ parameters are obtained using standard single-qubit characterization techniques, such asRabi and Ramsey oscillations and frequency sweep of the resonators. We also characterized theexperimental setup, including finding the working point of a Josephson Parametric Amplifierand the coupler between the two qubits. We solve the linear differential equations that modelthe resonator, in order to design a high-fidelity, single-shot qubit-measurement pulse shape,which actively empties the cavity. Using this pulse, we achieve a readout assignment fidelity of99.9%. The readout is formed in real-time using template matching. In addition, we implementa conditional reset of the qubit’s state in 1.4 μs, which resets the excited state population from5.4% to 0.5%. We simulate the cavity using QuTip to further optimize the readout pulse.Furthermore, we characterize the third energy level of the qubit to implement a qutrit readoutand observe a second excited state population of 0.3%, in accordance with theory. Finally,we implement the iSwap gate that, together with single-qubit gates, constitute a set of universalquantum gates, where we swap the 95.4% of the quantum state between the qubits in 690 ns. Allexperiments, including the pulse events and synchronization of the readout and feedback, wereperformed using a digital microwave platform based on a radio-frequency-on-a-chip system,and implemented using a Python interface. / Vi manipulerar två supraledande kvantbitar med digital mikrovågselektronik. Vi utgår frånderas karakterisering och utvecklar en realtidsåterställningsschema och implementerar iSwap-grinden. Kvantbitarnas parametrar erhålls med standardtekniker för karakterisering av enskildakvantbitar, såsom Rabi- och Ramsey-svängningar och frekvenssvep av resonatorerna. Vikaraketeriserar även den experimentella uppställningen, där vi finner arbetspunkten för enJosephson-parametrisk förstärkare, samt kopplaren mellan de två kvantbitarna. Vi löser delinjära differentialekvationerna som modellerar resonatorn, i syfte att designa en pulsformför en enkelmätning av en kvantbit med hög tillförlitlighet som aktivt tömmer kaviteten.Med denna puls uppnår vi en avläsningstillförlitlighet på 99,9 %. Avläsningspulsen bildas irealtid med hjälp av mallmatchning. Därtill implementerar vi en villkorlig återställning avkvantbitens tillstånd på 1,4 μs, vilket återställer den exciterade tillståndspopulationen från 5,4 %till 0,5 %. Vi simulerar kaviteten med QuTip för att ytterligare optimera avläsningspulsen.Dessutom karakteriserar vi den tredje energinivån på kvantbiten för att implementera enså-kallad qutrit-avläsning och observerar en andraexciterad tillståndspopulation på 0,3 %,i enlighet med teorin. Slutligen implementerar vi iSwap-grinden som, tillsammans medgrindarna för enskilda kvantbitar, utgör en uppsättning universella kvantgrindar, är vi byter95,4 % av kvanttillståndet mellan våra kvantbitarna på 0,6 μs. Alla experiment, såsompulshändelserna och synkroniseringen av avläsningspulsen och återkopplingspulsen, utfördesmed hjälp av en digital mikrovågsplattform, baserad på ett radiofrekvens-på-ett-chip-system,och implementerades med ett Python-gränssnitt.
4

Rekonfigurovatelný generátor 5G NR signálů na RFSoC FPGA / Reconfigurable 5G NR signal generator on RFSoC FPGA

Indrák, Dominik January 2020 (has links)
This work deal with simulation of basic structure of OFDM modulator and demodulator of the upcoming standard 5G NR. In MATLAB are simulated basic parts including modulation, reference signal inserting, Fourier transform, cyclic prefix inserting, AWGN and multi-path propagation. In this work is proposed implementation of the modulator and demodulator into RFSoC board and his configuration. Designed generator is implemented with the use of STEMLab RedPitaya platform. In Matlab software is generated 5G OFDM signal used to transmitt. Received signal is evaluated in Matlab software.
5

On Algorithmic Design Methodologies, Heterogenous RFSoC/GPU Beamformers, and Cryogenic Antenna Efficiency Evaluation for Phased Array Receivers in Radio Astronomy

Burnett, Mitchell C. 26 June 2023 (has links) (PDF)
Modern radio astronomy’s demand for high sensitivity and wide fields of view is met through innovations that reduce receiver system noise temperatures and integrate technology supporting parallel processing and larger instantaneous bandwidths. The advanced L-band phased array camera for astronomy (ALPACA) is a fully cryogenic 69 dual-polarized dipole PAF and digital beamformer back end for the Green Bank Telescope. This instrument will form 40 dual-polarized beams yielding a 0.35 sq. deg field of view on the sky with a 305.2 MHz processing bandwidth. The target system noise temperature is 27 K. A structured technique to map critically sampled and oversampled polyphase filter banks (PFBs) onto a systolic array for implementation on a field programmable gate array (FPGA) is shown. This method provides unique insights into the operation of these algorithms. A case study for an oversampled PFB operating at 666.67 Msps shows that these designs effectively utilize FPGA resources, maintain high-throughput, and are flexible solutions for varied application requirements. A new class of FPGA, the Radio Frequency System-on-Chip (RFSoC), is integrated as a full-functioning software-defined hardware platform in an open-source signal processing toolchain. This provides astronomers with essential hardware for contemporary scientific research. The demonstration for an experimental technique for measuring antenna radiation efficiency using the antenna Y factor method is presented. The noise contribution of the ALPACA dipole when operating at cryogenic temperatures is estimated. Our findings show that the antenna is expected to contribute less than 1 K to the instrument’s overall system noise temperature. Research contributions of this work are: the integration of new high-performance digital hardware in radio astronomical PAF digital back ends, an open-source RFSoC signal processing development toolchain, an oversampled PFB using an FPAG-based systolic array design, and estimating the cryogenic noise temperature of an ALPACA dipole from its radiation efficiency.
6

RFI Mitigation and Discrete Digital Signal Processing RFSoC Algorithm Implementations for Radio Astronomy and Wideband Communication Systems

Ward, Devon Christopher 28 March 2024 (has links) (PDF)
Due to the massive increase of active transmitters broadcasting over wideband frequencies, such as 5G wireless systems, LEO/MEO satellites, satellite constellations, and the increase of IoT devices in the average home, the radio frequency spectrum is becoming more and more congested by interference. Passive receivers face additional challenges due to the growing use of wideband frequency transmissions aimed at boosting communication system throughput. As a result, passive receivers must adopt more robust and intricate techniques to mitigate radio frequency interference. A proposed RFI removal system, known as the true time delay Hadamard projection algorithm, has been introduced in previous work to eliminate a single RFI source while preserving a narrowband signal of interest. An RF frontend is developed to assess the effectiveness of the Hadamard projection algorithm implemented on an RFSoC ZCU216. Additionally, the TTD Hadamard projection algorithm is expanded to enable the cancellation of multiple RFI sources rather than just a single source for a uniform linear array and a uniform rectangular array. Over-the-air tests are conducted to verify the performance of the interference cancellation algorithms and demonstrate the algorithms' ability to preserve the signals of interest while removing the wideband interference. Multiple algorithms are proposed to estimate the time delays used by the interference cancellation algorithm to effectively eliminate wideband interference. These algorithms address diverse scenarios encompassing interference sources ranging from strong to weak SNR. Detailed reports of algorithm performance provide insights into their effectiveness and suitability across specific interference conditions.

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