The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that executing processes tend to be executed again. This property is termed executive temporal locality, and it can be exploited by migration systems to accelerate RTL simulation. In this dissertation, process migration is first formally modeled using Finite State Machines (FSMs). Upon FSMs are built programs, processes, migration realms, and the migration of process state within a realm. From this model, a taxonomy of migration realms is developed. Second, process migration is applied to the RTL simulation of digital circuits. The canonical form of an RTL process is defined, and transformations of HDL code are justified and demonstrated. These transformations allow a simulator to identify basic active units within the simulation and combine them to balance the load across a set of processors. Through the use of input monitors, executive locality of reference is identified and demonstrated on a set of six RTL designs. Finally, the implementation of a migration system is described which utilizes Virtual Machines (VMs) and Real Machines (RMs) in existing FPGAs. Empirical and algorithmic models are developed from the data collected from the implementation to evaluate the effect of optimizations and migration algorithms. / Ph. D.

RISC-V is growing in popularity as a free and open RISC Instruction Set Architecture (ISA) in academia and research. Also, the openness, simplicity, extensibility, and modularity, among its advantages, make it more and more used by designers in industry. The aim of this thesis is to design an open-source RISC-V processor. The development of this RISC-V processor was based on the prototype which was made in the course IL2232 Embedded Systems Design Project (SoI-CMOS Design group), against an experimental high-temperature SoC CMOS process. SystemVerilog was used for RTL coding. ModelSim was used for RTL simulation. Genus was used for digital synthesis and Innovus was used for digital place & route. The thesis concludes that this RISC-V processor can run the compiled C-code which has been produced by the virtual platform tool Imperas OVP. The instruction set RV32IM is the Instruction Set base for this processor. Through simulation, the CPI of this RISC-V processor can be collected while running different benchmark programs developed in two parallel Master thesis to this one. To a certain extent, it can reflect the performance of the processor. However, the actual execution time needs to be tested by loading the processor to the hardware. This part will not be discussed in this thesis but is left for future work. The gate count is collected by digital synthesis and the corresponding area is collected after digital place & route. / RISC-V växer i popularitet som en gratis och öppen RISC ISA inom akademi och forskning. Öppenheten, enkelheten, utbyggbarheten och modulariteten, bland dess fördelar, gör att den används mer och mer av designers inom industrin. Syftet med denna avhandling är att designa en RISC-V-processor med öppen källkod. Utvecklingen av denna RISC-V-processor baserades på prototypen som gjordes i kursen IL2232 Embedded Systems Design Project (SoI-CMOS Design group). Mot en experimentell högtemperatur, SoC CMOS-process diskuteras. SystemVerilog användes för RTL-kodning. ModelSim användes för RTL-simulering. Genus användes för digital syntes och Innovus användes för digital plats & rutt. Avhandlingen drar slutsatsen att denna RISC-V-processor kan köra den kompilerade C-koden som har producerats av det virtuella plattformsverktyget Imperas OVP. Instruktionsuppsättningen RV32IM är instruktionsuppsättningens bas för denna processor. Genom simulering kan CPI för denna RISC-V-processor samlas in samtidigt som man kör olika benchmarkprogram utvecklade i två parallella masteruppsatser till denna. Till viss del kan det spegla processorns prestanda. Den faktiska exekveringstiden måste dock testas genom att ladda processorn till hårdvaran. Denna del kommer att diskuteras i denna uppsats men lämnas för framtida arbete. Grindräkningen samlas in genom digital syntes och motsvarande yta samlas in efter den digitala platsen & rutten.