With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this thesis, we present a radiation hardened PLL design. Each of the components of this design-the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the charge pump/loop filter-are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our design uses two VCOs (with cross-coupled inverters) and charge pumps, so that a strike on any one is compensated by the other. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our SPICE-based results demonstrate that after exhaustively striking all circuit nodes, the worst case jitter of our hardened PLL is just 37.4 percent. In the worst case, our PLL returns to the locked state in 2 cycles of the VCO clock, after a radiation strike. These numbers are significant improvements over those of the best previously reported approaches.

After ten years of massive success, the Large Hadron Collider (LHC) at CERN is going for an upgrade to the next phase, The High Luminosity Large Hadron Collider (HL-LHC) which is planned to start its operation in 2029. This is expected to have a fine boost to its performance, with an instantaneous luminosity of 5.0×1034 cm-2s -1 (ultimate value 7.5×1034 cm-2s -1 ) with 200 average interactions per bunch crossing which will increase the fluences up to more than 1016 neq/ cm2 , resulting in high radiation damage in ATLAS detector. To withstand this situation, it was proposed to make the innermost layer with 3D silicon sensors, which will have radiation tolerance up to 2×1016 neq/cm2 with a Total Ionization Dose of 9.9 MGy. Two-pixel geometries have been selected for 3D sensors, 50 × 50 μm2 for Endcap (ring), which will be produced by FBK (Italy) and SINTEF (Norway), and 25 × 100 μm2 for Barrel (stave), will be produced by CNM (Spain). A discussion is made in this thesis about the production of FBK on both geometries, as they have made a breakthrough with their Stepper lithography process. The yield improved, specifically for the geometry 25 × 100 μm2 with two electrode readouts, which was problematic in the mask aligner approach. Their sensors were characterized electrically at waferlevel as well as after integration with RD53a readout chip (RoC) on single-chip cards (SCC) and were verified against Innermost Tracker criteria. The SCCs were sent for irradiation up to 1×1016 neq/cm2 and were tested under electron test beam, and a hit efficiency of 97% was presented. Some more SCCs have been sent to Los Alamos for irradiating them up to 1.5×1016 neq/cm2 fluence. As the 3D sensors will be mounted as Triplets, a discussion is also made on their assembly and QA/QC process. A reception testing and electrical testing setup both at room temperature and the cold temperature was made and discussed, with results from some early RD53a RoC-based triplets. The pre-production sensors are already evaluated, and soon they will be available bump-bonded with ITkPixV1 RoC for further testing.

The Large Hadron Collider at CERN is scheduled to undergo upgrades in 2026-2028 to significantly increase its luminosity. These upgrades, while providing the experiments with a higher collision rate, pose a number of challenges to the design of the hardware and software in the detectors. The Tile Calorimeter (a scintillating sampling calorimeter read out by photomultiplier tubes) at the ATLAS experiment will have its read-out electronics completely replaced to enable performance and reliability improvements.  Advances in electronics, new requirements due to the luminosity upgrade as well as lessons learned from the current readout scheme drove development with the goals to partition the readout into small independent units with full granularity readout and a robust mitigation strategy for radiation induced errors. To verify the functionality of the new system while retaining backward compatibility a "Demonstrator'' has been developed to emulate the current functionality while using new and improved hardware. The board responsible for managing digitized calorimeter data and communicating with the off-detector electronics, called the DaughterBoard, is the main focus of this thesis. It has two electrically isolated sides for redundancy where each side consists of voltage regulators, two optical transceivers, a GigaBit transceiver chip (for clocking and configuration) and a Kintex FPGA for data processing. In addition to data management and transmission, the FPGA (and every other component) needs to be able to withstand the effects of radiation both in terms of total dose (ionization and displacement damage) and due to single event effects. The DaughterBoard was developed with this in mind and has undergone several radiation tests during its development to verify reliability and fault tolerance. / CERN

This thesis evaluates the suitability of silicon-germanium technology for electronic systems intended for extreme environments, such as ambient temperatures outside of military specification (-55 degC to 125 degC) range and intense exposures to ionizing radiation. Silicon-germanium devices and circuits were characterized at cryogenic and high-temperatures (up to 300 degC) and exposed to ionizing radiation, providing empirical evidence that silicon-germanium is an excellent platform for terrestrial and space-based electronic applications.