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This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 µm CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.

The objective of the research presented in this dissertation is to explore the achievable dynamic range limits in high-performance RF front-ends designed using SiGe HBTs, with a focus on complementary (npn + pnp) SiGe technologies. The performance requirements of RF front-ends are high gain, high linearity, low dc power consumption, very low noise figure, and compactness. The research presented in this dissertation shows that all of these requirements can easily be met by using complementary SiGe HBTs. Thus, a strong case is made in favor of using SiGe technologies for designing high dynamic range RF front-ends. The contributions from this research are summarized as follows: 1. The first-ever comparison study and comprehensive analysis of small-signal linearity (IIP3) for npn and pnp SiGe HBTs on SOI. 2. A novel comparison of large-signal robustness of npn and pnp SiGe HBTs for use in high-performance RF front-ends. 3. A systematic and rigorous comparison of SiGe HBT compact models for high-fidelity distortion modeling. 4. The first-ever feasibility study of using weakly-saturated SiGe HBTs for use in severely power constrained RF front-ends. 5. A novel X-band Low Noise Amplifier (LNA) using weakly-saturated SiGe HBTs. 6. Design and comprehensive analysis of RF switches with enhanced large-signal linearity. 7. Development of novel methods to reduce crosstalk noise in mixed-signal circuits and the first-ever analysis of crosstalk noise across temperature. 8. Design of a very high-linearity cellular band quadrature modulator for use in base-station applications using first-generation complementary SiGe HBTs.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

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SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wireline transceiver in SiGe BiCMOS technology. This work also includes design and testing of a charge amplification channel front-end intended to act as the interface between a piezoelectric sensor and an ADC. An additional feature is the design and testing of a 50 Ohm output buffer utilized for testing of components in a lab setting.

The communication industry leverages technical advancements in various domains, such as semiconductors, optics, signal processing, and integrated circuits, leading to remarkable evolution over the last decades. This progress paves the way for ever-expanding networks and systems that demand more information capacity, which results in exponential data growth. Unique wireless concepts and technologies are emerging to enable next-generation communication. This dissertation explores the techniques and architectures to realize massive MIMO, extreme bandwidths through channel aggregation, TeraHertz band utilization, and the use of III-V technologies to enhance performance via heterogeneous integration, ultimately maintaining ubiquitous connectivity. The first chapter discusses the various recent research trends in communication technologies: the allocation of millimeter-wave frequencies to benefit from the broad available spectrum, 2D scalability to enhance system performance and overcome link budget requirements, MIMO, and channel aggregation concepts to extend data capacity, heterogeneous integration to exploit benefits of various technologies, transitioning to THz region to improve spectrum efficiencies and diversify applications. The key insight of this dissertation is that we implement distinct system/architecture-level solutions to achieve target data rates for the continuation of the advancements in communication technologies. The first project in this thesis presents a MIMO receiver array that utilizes a simplified single-wire interface for IF/LO signals that overcomes the high-frequency input/output distribution complexity for large-scale systems. Code-domain multiplexing is performed on the single-wire interface to preserve and transfer individual information of all channels. The four-channel receiver prototype that operates at 28GHz and achieves >20dB channel-to-channel isolation is presented. Digital beamforming and MIMO capability of the array have been demonstrated. The later chapter of this dissertation discusses the fundamental limitation of code-domain multiplexing, the trade-off between isolation and interface bandwidth, and explains our novel frequency-domain multiplexing approach. A harmonic rejection mixer has been used to generate the required multiple LO tones to de-multiplex individual channel signals simultaneously. A 60GHz four-element MIMO transmitter prototype is presented, and its functionalities are illus- trated. The prototype achieves >30dB channel-to-channel isolation for an overall bandwidth of 10GHz, supports 64QAM modulated signals, and is capable of performing MIMO beamforming. Next, benefiting from our research experience on FDM and HRM, we proposed a frequency- interleaving architecture for wideband channel aggregated systems. We divided the total IF band- width into four sub-channels and individually up/down-converted them to the baseband, alleviating the requirements of Analog-to-Digital/Digital-to-Analog Converters. HRM is utilized to generate multiple LO frequencies, as in the FDM-based transmitter work. The prototype system comprises two baseband channelizer ICs (TX/RX) and two mm-wave beamformer ICs (TX/RX), where channelizers perform FI aggregation and despread IF signals, and beamformers are responsible for beam steering and tapering. The four-channel transceiver chipset operates at 60GHz, provides >25dB isolation for an overall IF bandwidth of 8GHz, and supports 64QAM modulated signals. The next section of the dissertation presents a wideband sub-THz transceiver phased array system with SWI. We propose a D-band scalable 16-element transceiver system with novel front- end block designs to satisfy link budget requirements and enable high data rates and complex modulation data transfer. The prototype consists of one phased array transmitter and one phased array receiver. Simulated performance shows that the receiver system has ∼34dB gain, -30dBmIP1dB with a minimum 5.4dB NF. While, transmitter achieves ∼34dB gain with a 9dBm OP1dB. The last chapter looks beyond CMOS technology and presents front-end blocks at III-V technologies. Two circulator prototype designs with different architectures are implemented using GaN technology. Better linearity performance is targeted by leveraging heterogeneous integration, using GaN devices for the core and CMOS circuitry for clock generation. In addition, a future direction for THz systems, GaN-assisted beamformer architecture, is presented.

Time Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the object is collected by a “light-bucket” detector, and the resulting electrical signal is digitized and subjected to a series of signal processing operations, including an all-critical averaging of the amplitude and phase of a number of narrow-band signals. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2014. / FAU Electronic Theses and Dissertations Collection

The development of multi-standard wireless communication systems with low cost and high integration is continuously requested and accompanied by the explosive growth of the wireless communication market. Although CMOS technology can provide most building blocks in RF transceivers, the implementation of CMOS RF power amplifiers is still a challenging task. The objective of this research is to develop design techniques to implement fully-integrated multi-mode power amplifiers using CMOS technology. In this dissertation, a load modulation technique with tunable matching networks and a pre-distortion technique in a multi-stage PA are proposed to support multi-communication standards with a single PA. A fully-integrated dual-mode GSM/EDGE PA was designed and implemented in a 0.18 um CMOS technology to achieve high output power for the GSM application and high linearity for the EDGE application. With the suggested power amplifier design techniques, fully-integrated PAs have been successfully demonstrated in GSM and EDGE applications. In Addition to the proposed techniques, a body-switched cascode PA core is also proposed to utilize a single PA in multi-mode applications without hurting the performance. With the proposed techniques, a fully-integrated multi-mode PA has been implemented in a 0.18 um CMOS technology, and the power amplifier has been demonstrated successfully for GSM/EDGE/WCDMA applications. In conclusion, the research in this dissertation provides CMOS RF power amplifier solutions for multiple standards in mobile wireless communications with low cost and high integration.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.