米勒補償是現今最被廣泛使用的頻率補償方法之一。其極點分離現象為雙級放大器供簡易而又可靠的穏定作用。可是，隨着亞微米 CMOS 技術及低電壓電路設計的興起，高增益同時又寬頻寬的放大器設計變得愈來愈困難。雖然多階段方式能實現高增益的放大器規格，但其頻寬會隨之縮窄，頻率補償亦會變得複雜及困難。 / 在過去，很多學術硏究報告都提出了不少方法去解決多階段放大器頻寬縮窄的問題，但這些方法往往離開複雜的頻率補償技巧及電路結構。為了根本性地解決此問題，本論文會提出一個虛擬雙階段放大器的設計。此放大器設計利用了兩個低增益階段來放大進入第二階段前的訊號振幅，從而放進整個放大器的頻寬及增益。由於其簡單的結構，這個設計仍然能夠採用穏定可靠的簡易米勒補償方式來穏定整個放大器。 / 這個設計由CMOS 180nm（互補式屬-氧化層-半導體180納米）技術製成。實驗結果證實了其高增益及寬頻寬的效能。另外，這果放大器亦同時應用在一個低通濾波器的實現上，用以證明其實際應用上的用途。實驗結果證實利用該放大器實現的低通濾波器比用一般雙段放大器的功率消耗減少近 45%。 / Miller compensation is one of the most widely adopted frequency compensation techniques for two-stage amplifier design. With its pole-splitting behavior achieved by connecting a capacitor between the output nodes of the two gain stages, Miller compensation provides a simple and reliable stabilizing function to two stage amplifiers. However, with the advance of sub-micron CMOS technology and low-voltage circuit designs, high-gain and wide-bandwidth amplifier design becomes more difficult. Although multi-stage amplifiers can be used to attain high-gain specification, the bandwidth will be degraded dramatically and the frequency compensation scheme becomes much more complicated. / To solve the problem, several researches have been done to improve the frequency response of multi-stage amplifiers so as to achieve high-gain and wide-bandwidth specifications simultaneously. However, these always result in the increase of circuit complexity and more complicated frequency compensation techniques. / In this thesis, a virtual two-stage Miller compensated amplifier will be proposed. By using two small gain stages, the characteristics of a conventional two-stage Miller compensated amplifier can be retained due to the low output impedance of the two gain stages. The small gain stages boost the input signal amplitude of the second stage such that the generated small-signal output current can be increased significantly. This results in wider signal bandwidth and higher voltage gain. / The proposed design has been fabricated in UMC CMOS 0.18μm technology. Experimental results have verified the concept. From the measurement, the unity-gain frequency of the proposed design is better than the conventional design by 4 times. Moreover, the voltage gain is improved by about 20dB. The current consumption is 124.76μA which is the nearly the same as the conventional design. / In order to show the improvement in real applications, the proposed amplifier has been applied to a fifth-order low-pass filter with corner frequency of 50kHz. Under the same performance, the power consumption of the filter using the proposed amplifier can be reduced by about 45%. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Poon, Hiu Ching. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract --- p.i / Acknowledgments --- p.iv / Table of Content --- p.v / List of Figures --- p.vii / List of Tables --- p.xi / Symbols Declarations --- p.xii / Chapter Chapter 1 --- Background Information / Chapter 1.1 --- High-Gain Amplifier and its Application with Negative Feedback Configuration --- p.1-1 / Chapter 1.2 --- High-Gain Amplifier Design and the Tradeoffs --- p.1-6 / Chapter 1.3 --- High-Gain Amplifier Implementations --- p.1-8 / Chapter 1.4 --- Contribution and Outlines of the Thesis --- p.1-15 / References --- p.1-16 / Chapter Chapter 2 --- Analysis of Frequency Compensation Techniques / Chapter 2.1 --- Simple Miller Compensation --- p.2-1 / Chapter 2.2 --- Miller Compensation with Null Resistor --- p.2-10 / Chapter 2.3 --- Miller Compensation with Multipath Zero Cancellation --- p.2-13 / Chapter 2.4 --- Nested Miller Compensation --- p.2-15 / Chapter 2.5 --- Advanced Frequency Compensation Techniques --- p.2-17 / Chapter 2.6 --- Conclusion of Chapter --- p.2-20 / References --- p.2-22 / Chapter Chapter 3 --- Proposed Amplifier Design / Chapter 3.1 --- Gain Tolerance --- p.3-1 / Chapter 3.2 --- Adjustments on Simple Miller Compensated Two-Stage Amplifier --- p.3-3 / Chapter 3.3 --- Introducing the Small Gain Stage --- p.3-4 / Chapter 3.4 --- Concept of the Proposed Virtual Two-Stage Miller Compensated Amplifier --- p.3-7 / Chapter 3.5 --- Comparisons with Bandwidth Enhanced Miller Compensated Two-Stage Amplifier --- p.3-9 / Chapter 3.6 --- Proposed Virtual Two-Stage Amplifier with Simple Miller Compensation --- p.3-13 / Chapter 3.7 --- Design Considerations and Expected Performance --- p.3-15 / Chapter 3.8 --- Experimental Result --- p.3-18 / Chapter 3.9 --- Conclusions of Chapter --- p.3-31 / References --- p.3-32 / Chapter Chapter 4 --- Implementation of the Low-Pass Filter / Chapter 4.1 --- Implementation of the Low-Pass Filter --- p.4-1 / Chapter 4.2 --- Experimental Result --- p.4-4 / Chapter 4.3 --- Conclusion of Chapter --- p.4-7 / Reference --- p.4-8 / Chapter Chapter 5 --- Conclusion and Future Work / Chapter 5.1 --- Conclusion of Thesis --- p.5-1 / Chapter 5.2 --- Suggestion for Future Work --- p.5-2

This thesis is concerned with the design and implementation of radio frequency (RF) power amplifiers and micro-electromechanical systems---namely MEMS varactors. This is driven by the many wireless communication systems which are constantly moving towards increased integration, better signal quality, and longer battery life. / The power amplifier consumes most of the power in a receiver/transmitter system (transceiver), and its output signal is directly transmitted by the antenna without further modification. Thus, optimizing the PA for low power consumption, increased linearity, and compact integration is highly desirable. / Micro-electromechanical systems enable new levels of performance in radio-frequency integrated circuits, which are not readily available via conventional IC technologies. They are good candidates to replace lossy, low Q-factor off-chip components, which have traditionally been used to implement matching networks or output resonator tanks in class AB, class F, or class E power amplifiers. The MEMS technologies also make possible the use of new architectures, with the possibility of flexible re-configurability and tunability for multi-band and/or multi-standard applications. / The major effort of this thesis is focused on the design and fabrication of an RF frequency class AB power amplifier in the SiGe BiCMOS 5HP technology, with the capability of being tuned with external MEMS varactors. The latter necessitated the exploration of wide-tuning range MEMS variable capacitors, with prototypes designed and fabricated in the Metal-MUMPS process. / An attempt is made to integrate the power amplifier chip and the MEMS die in the same package to provide active tuning of the power amplifier matching network, in order to keep the efficiency of the PA constant for different input power levels and load conditions. / Detailed simulation and measurement results for all circuits and MEMS devices are reported and discussed.

No description available.

Widely used design techniques for radio frequency power amplifiers yield results which are approximate; the initial design is usually refined by applying trial-and-error procedures in the laboratory. More accurate design techniques are complicated in their application and have not gained acceptance by practicing engineers. A new design technique for VHF linear power amplifiers using bipolar junction transistors is presented in this report. This design technique is simple in its application but yields accurate results. The design technique is based upon a transistor model which is simple enough to be useful for design, but which is sufficiently accurate to predict performance at high frequencies. Additionally, the model yields insight into many of the processes which take place within the typical RF power transistor. The fundamental aspect of the model is the inclusion of charge storage within the transistor base. This charge storage effect gives rise to a nearly sinusoidal collector current waveform, even in a transistor which ostensibly is biased for class B or nonsaturating class C operation. Methods of predicting transistor input and output impedances are presented. A number of other topics related to power amplifier measurement and design are also included. A unique measurement approach which is ideally suited for use with power amplifiers is discussed. This measurement approach is a hybrid of the common S-parameter measurement technique and the "load-pull" procedure. Practical considerations such as amplifier stability, bias network design, and matching network topology are also included in the report. / Ph. D.

The demand for higher frequency applications is largely driven by bandwidth. The evolution of circuits in the microwave and millimeter frequency ranges always demands higher performance and lower cost as the technology and specification requirements evolve. Thus the development of new processes addressing higher frequencies and bandwidth requirements is essential to the growth of any semiconductor company participating in these markets. There exist processes which can perform in the higher frequency design space from a technical perspective. However, a cost effective solution must complement the technical merits for deployment. Thus a new 0.15 um optical lithography pHEMT process was developed at TriQuint Semiconductor to address this market segment. A 40 GHz power amplifier has been designed to quantify and showcase the capabilities of this new process by leveraging the existing processing knowledge and the implementation of high frequency scalable models. The three stage power amplifier was designed using the TOM4 scalable depletion mode FET model. The TriQuint TQP15 Design Kit also implements microstrip transmission line models that can be used for evaluating the interconnect lines and matching networks. The process also features substrate vias and the thin film resistor and MIM capacitor models which utilize the capabilities of the BCB process flow. During the design stage we extensively used Agilent ADS program for circuit and EM simulation in order to optimize the final design. Special attention was paid to proper sizing of devices, developing matching circuits, optimizing transmission lines and power combining. The final design exhibits good performance in the 40 GHz range using the new TQP15 process. The measured results show a gain of greater than 13 dB under 3 volt drain voltage and a linear output power of greater than 28 dBm at 40 GHz. The 40 GHz power amplifier demonstrates that the new process has successfully leveraged an existing manufacturing infrastructure and has achieved repeatability, high volume manufacturing, and low cost in the millimeter frequency range.

An abstract of the thesis of Bosi Chen for the Master of Science in Electrical and Computer Engineering presented Aug 1st, 2012. Title: Spectrum Regrowth for OFDM-based LTE and WiMAX Systems. In OFDM-based (Orthogonal Frequency Dimension Multiplexing) LTE (Long Term Evolution) and WiMAX (Worldwide Interoperability for Microwave Access) Systems, one of the critical components is the RF power amplifier. With current technologies, RF power amplifiers are not perfectly linear. The nonlinearity of an RF power amplifier is one of the main concerns in RF power amplifier design. The nonlinearity control is described by the out-of-band power emission levels, and the nonlinearity of an RF power amplifier is usually described by IP3 (the third-order intercept point). However, there is need of a clear relationship or expression between the out-of-band power emission level and IP3 for LTE and WiMAX Systems, which helps the RF designers to choose components. This thesis presents the analysis of the nonlinear effect of an RF amplifier in LTE and WiMAX Systems, and the derivation of the expressions for the estimated out-of-band emission levels for LTE and WiMAX signals in terms of IP3 and the power level of the signal. The result will be helpful for RF engineers in the design and test of RF power amplifiers in LTE and WiMAX Systems.

Next generation mobile communication systems require the use of linear RF power amplifier for higher data transmission rates. However, linear RF power amplifiers are inherently inefficient and usually require additional circuits or further system adjustments for better efficiency. This dissertation focuses on the development of new efficiency enhancement schemes for linear RF power amplifiers. The multistage Doherty amplifier technique is proposed to improve the performance of linear RF power amplifiers operated in a low power level. This technique advances the original Doherty amplifier scheme by improving the efficiency at much lower power level. The proposed technique is supported by a new approach in device periphery calculation to reduce AM/AM distortion and a further improvement of linearity by the bias adaptation concept. The device periphery adjustment technique for efficiency enhancement of power amplifier integrated circuits is also proposed in this work. The concept is clearly explained together with its implementation on CMOS and SiGe RF power amplifier designs. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. In addition to the efficiency enhancement of power amplifiers, a scalable large-signal MOSFET model using the modified BSIM3v3 approach is proposed. A new scalable substrate network model is developed to enhance the accuracy of the BSIM3v3 model in RF and microwave applications. The proposed model simplifies the modeling of substrate coupling effects in MOS transistor and provides great accuracy in both small-signal and large-signal performances.

With the move of the broadband cellular network towards 5G taking off and the preparatory work on 6G and beyond starting, the need for low-complexity, low-power, and high-performance frequency synthesis using Phase-Locked Loop (PLL)s increases. As we get deeper into the mm-wave frequencies and push towards frequencies in the order of 50-70 GHz design challenges with existing PLL architectures, such as limited technology scaling and limited in-band noise performance become more apparent. Other designs have tried overcoming these problems, for example by using single-bit phase detection at the cost of increased complexity when trying to control the bandwidth, or designing the loop with lower bandwidth to suppress in-band noise at the cost of requiring a lower noise and thus more power hungry oscillator. This thesis proposes a new Phase-locked loop architecture implemented in a 22nm node to combat these issues, utilizing a Pulse-Shrinking Time-To-Digital Converter (PS-TDC) offering sub-pico-second resolution with minimal power consumption in lock. The results found in this thesis have shown the viability of such a design, offering good in-band performance, allowing for wide bandwidth, and the use of a cheaper low-power Digital-Controlled Oscillator (DCO). The PS-TDC architecture combined with control logic implemented in this project can drastically decrease power consumption in lock while being able to compensate for process variations to optimize jitter performance. Additionally, by utilizing a Phase-Frequency Detector (PFD) and gear-shifting logic it has been shown that robust and fast locking can be achieved. / Med övergången till 5G i mobila bredbandsnätverk och förberedelserna för 6G på gång ökar behovet av lågkomplexa, lågeffekts- och högpresterande frekvenssyntes. När vi beger oss djupare in i millimetervågsfrekvenserna och strävar efter frekvenser uppemot 50-70 GHz blir designutmaningar med befintliga faslåsta loopar, såsom begränsad teknologiskalning och dålig prestanda för inband-brus, alltmer tydliga. Andra designer har försökt att övervinna dessa problem genom att till exempel använda enbitars fasdetektion till priset av ökad komplexitet vid styrning av systemets bandbredd, eller genom att designa loopen med lägre bandbredd för att vidare dämpa inband-brus, vilket kommer till priset av en oscillator med lägre brus och därmed högre effektförbrukning. Denna avhandling föreslår en ny arkitektur för faslåsta loopar för att överkomma dessa problem genom att använda en pulskrympande tids-till-digital omvandlare som erbjuder sub-pikosekunds upplösning med minimal effektförbrukning när frekvensen är låst. Resultaten som presenteras i denna avhandling har visat att en sådan design är möjlig, med god in-band prestanda, möjlighet till hög bandbredd och därmed användning av en billigare lågeffekt DCO. Den pulsskalande TDC-arkitekturen i kombination med kontrolllogik implementerad i detta projekt kan dramatiskt minska effektförbrukningen när frekvensen är låst, samtidigt som den kan kompensera för processvariationer för att optimera jitterprestanda. Sist har det visats att en robust och snabb låsning av frekvensen kan uppnås genom att använda en PFD.