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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

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Showing 1 to 2 of 2 (0.017 seconds)

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1

High Level Model of IEEE 802.15.3c Standard and Implementation of a Suitable FFT on ASIC

Ahmed, Tanvir January 2011 (has links)
A high level model of HSIPHY mode of IEEE 802.15.3c standard has been constructedin Matlab to optimize the wordlength to achieve a specific bit error rate (BER) depending on the application, and later an FFT has been implemented for different wordlengths depending on the applications. The hardware cost and power is proportional to wordlength. However, the main objective of this thesis has been to implement a low power, low area cost FFT for this standard. For that the whole system has been modeled in Matlab and the signal to noise ratio (SNR) and wordlength of the system have been studied to achieve an acceptable BER. Later an FFT has been implemented on 65nm ASIC for a wordlength of 8, 12 and 16 bits. For the implementation, a Radix-8 algorithm with eight parallel samples has been adopted. That reduce the area and the power consumption significantly compared to other algorithms and architectures. Moreover, a simple control has been used for this implementation. Voltage scaling has been done to reduce thepower. The EDA synthesis result shows that for 16bit wordlength, the FFT has 2.64 GS/s throughput, it takes 1.439 mm2 area on the chip and consume 61.51mW power.
WPAN
FFT
ASIC
Radix-8
Electrical engineering
Elektroteknik
2

Low-Power, Low-Cost, & High-Performance Digital Designs: Multi-bit Signed Multiplier design using 32nm CMOS Technology

Boppana, N V Vijaya Krishna 26 August 2022 (has links)
No description available.
Electrical Engineering
Computer Engineering
Digital Design
Digital Multiplier
Signed Multiplier
Low-power
Low-cost
High-performance
Modified Booth
Radix-8 structure
8 x 8
16 x 16
32 x 32
64 x 64
32nm CMOS Technology
Synthesize
Placement & Route (PnR)

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