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As demand for real-time image processing increases, the need to improve the efficiency of image processing systems is growing. The process of image segmentation is often used in preprocessing stages of computer vision systems to reduce image data and increase processing efficiency. This dissertation introduces a novel image segmentation approach known as leap segmentation, which applies a flexible definition of adjacency to allow groupings of pixels into segments which need not be spatially contiguous and thus can more accurately correspond to large surfaces in the scene. Experiments show that leap segmentation correctly preserves an average of 20% more original scene pixels than traditional approaches, while using the same number of segments, and significantly improves execution performance (executing 10x - 15x faster than leading approaches). Further, leap segmentation is shown to improve the efficiency of a high-level vision application for scene layout analysis within 3D scene reconstruction. The benefits of applying image segmentation in preprocessing are not limited to single-frame image processing. Segmentation is also often applied in the preprocessing stages of video analysis applications. In the second contribution of this dissertation, the fast, single-frame leap segmentation approach is extended into the temporal domain to develop a highly-efficient method for multiple-frame segmentation, called video leap segmentation. This approach is evaluated for use on mobile platforms where processing speed is critical using moving-camera traffic sequences captured on busy, multi-lane highways. Video leap segmentation accurately tracks segments across temporal bounds, maintaining temporal coherence between the input sequence frames. It is shown that video leap segmentation can be applied with high accuracy to the task of salient segment transformation detection for alerting drivers to important scene changes that may affect future steering decisions. Finally, while research efforts in the field of image segmentation have often recognized the need for efficient implementations for real-time processing, many of today’s leading image segmentation approaches exhibit processing times which exceed their camera frame periods, making them infeasible for use in real-time applications. The third research contribution of this dissertation focuses on developing fast implementations of the single-frame leap segmentation approach for use on both single-core and multi-core platforms as well as on both high-performance and resource-constrained systems. While the design of leap segmentation lends itself to efficient implementations, the efficiency achieved by this algorithm, as in any algorithm, is can be improved with careful implementation optimizations. The leap segmentation approach is analyzed in detail and highly optimized implementations of the approach are presented with in-depth studies, ranging from storage considerations to realizing parallel processing potential. The final implementations of leap segmentation for both serial and parallel platforms are shown to achieve real-time frame rates even when processing very high resolution input images. Leap segmentation’s accuracy and speed make it a highly competitive alternative to today’s leading segmentation approaches for modern, real-time computer vision systems.

Les systèmes embarqués, y compris les dispositifs, l’intergiciel et le logiciel pour la création de sous-systèmes intelligents capables de gérer le contrôle d’appareils électroniques, font de plus en plus partie de nos vies quotidiennes : ils sont intégrés dans des infrastructures de base, (par exemple dans la gestion des routes et des chemins de fer) et sont désormais utilisés en tant que technologies-clés par des millions d'applications logicielles chaque jour. En outre, l'évolution rapide et continue des systèmes embarqués modernes a provoqué de nouveaux défis. Par exemple, la conception des processus complexes qui causent des retards dans le temps de commercialisation et la conséquente augmentation des coûts globaux. Ces systèmes sont plus enclins aux erreurs et par conséquence il devient prioritaire de fournir aux concepteurs des outils effectifs et efficaces pour les aider à surmonter les difficultés liées à la conception des systèmes globales, pour la vérification et pour la validation. Cette thèse est la définition et le développement d'une méthodologie de modélisation basée sur le profil de MARTE et sur le profil de SysML dans un contexte avionique, et orientée à la réutilisation des composantes logicielles et à leur vérification. Cette thèse vise à discuter et illustrer aussi l'efficacité d’une stratégie basée sur la combinaison d’UML, MARTE (Modeling and Analysis of Real Type and Embedded Systems) et des langages SysML sur des étapes différentes de la modélisation d'un système embarqué / Embedded Systems, including devices, middleware and software for the creation of intelligent sub-systems able of monitoring and controlling appliances, are more and more part of our world everyday lives; they are included in the basic infrastructure of society such as roads and railways and are key technologies used by millions of people every day. Moreover the continuous rapid evolution of modern embedded systems has given rise to new challenges: such as increasingly complex design processes that cause delays in time to market and cause escalation of overall design costs. Additionally, these systems are more prone to containing errors, and it becomes more relevant to provide designers with effective tools to aid them in overcoming the difficulties related to the overall system design, verification and validation. This thesis contributes to the definition and to the development of a model based methodology grounded on the OMG’s MARTE profile (Modeling and Analysis of Real Type and Embedded Systems) and on SysML profile to model requirements targeting an avionic case study, with a particular attention to the reuse of the modelled components and to the benefits of their verification. This thesis aims at discussing and illustrating the effectiveness of using a combination of UML, MARTE and SysML languages at the different steps of the embedded system modelling efforts and to provide within this thesis a set of methodological guidelines/steps and an approach to create design model, stores and verify them

Ethernet Switches are widely used in real-time distributed systems as a solution to guarantee the real-time behavior in communication. In this solution there are still some limitations which are the important obstacles obtaining timeliness in the network. These limitations are the limited number of priority levels as well as the possibility of memory overruns with consequent messages. The mentioned limitations can be eliminated using a master/slave technique along with FTT paradigm. The FTT-SE protocol which is a technique based on the master/slave and FTT methods was proposed to overcome the mentioned limitations. However, the FTT-SE protocol has been investigated for a small network architecture with a single switch and master node. Extension of this solution to larger networks is still an open issue. Three different architectures were suggested to scale the FTT-SE to large scale network. In this thesis we propose a solution that extends the FTT-SEprotocol while keeping the real-time behavior of the network. In this solution, we divided the network into a set of sub-networks, each contains one switch, set of slave nodes and one master node that connected to the associated switch in the network. Moreover, the switches are connected together directly without gateways and form a tree topology network. The solution includes both synchronous and asynchronous traffic in the network. We also show that the timeliness of the traffic can still be enforced. Moreover, to validate the solution we have designed and implemented a simulator based on the Matlab/Simulink which is a tool to evaluate different network architecture using Simulink blocks. All transmission can be visualized by the ordinary Scope block in the Simulink. Moreover, the end-to-end delay for all messages is calculated after the simulation running to show the response time of the network. Furthermore, the response time analysis is done for both synchronous and asynchronous messages in this thesis according to the proposed solution. The results from simulation and the analysis are compared together to validate the investigations.

L'Ingénierie Dirigée par les Modèles (IDM) place les modèles au cœur des processus de d'ingénierie logicielle et système. L'IDM permet de maitriser la complexité des logiciels et d'améliorer la rapidité et la qualité des processus de développement. Le Model Driven Architecture (MDA) est une initiative de l'Object Management Group (OMG) définissant un cadre conceptuel, méthodologique et technologique pour la mise-en-œuvre de flots de conception basés sur l'IDM. Le MDA s'appuie particulièrement sur une utilisation intensive des formalismes normalisés par l'OMG pour la mise-en-œuvre des flots IDM (UML pour la modélisation, QVT pour les transformations, etc.). Ce travail s'intéresse à la sémantique d'exécution du langage UML appliqué à l'exécution de modèles des applications temps réel embarquées. Dans ce contexte, l'OMG propose une norme qui définit un modèle d'exécution pour un sous-ensemble d'UML appelé fUML (foundational UML subset). Ce modèle d'exécution définit une sémantique précise non ambigüe facilitant la transformation de modèles, l'analyse, l'exécution de modèles et la génération de code. L'objectif de cette thèse est d'étudier et mettre-en-œuvre un moteur d'exécution de modèles UML pour les systèmes temps réel embarqués en explicitant les hypothèses portant sur la sémantique d'exécution des modèles à un niveau d'abstraction élevé afin de permettre l'exécution d'un modèle le plus tôt possible dans le flot de conception de l'application. Pour cela, nous avons étendu le modèle d'exécution défini dans fUML, en apportant une contribution sur trois aspects importants concernant les systèmes temps réel embarqués : * Gestion de la concurrence: fUML ne fournit aucun mécanisme pour gérer la concurrence dans son moteur d'exécution. Nous répondons à ce problème par l'introduction d'un ordonnanceur explicite permettant de contrôler les différentes exécutions parallèles, tout en fournissant la flexibilité nécessaire pour capturer et simuler différentes politiques d'ordonnancements. * Gestion du temps : fUML ne fixe aucune hypothèse sur la manière dont les informations sur le temps sont capturées ainsi que sur les mécanismes qui les traitent dans le moteur d'exécution. Pour cela, nous introduisons une horloge, en se basant sur le modèle de temps discret, afin de prendre en compte les contraintes temporelles dans les exécutions des modèles. * Gestion des profils : les profils ne sont pas pris en compte par ce standard, cela limite considérablement la personnalisation du moteur d'exécution pour prendre en charge de nouvelles variantes sémantiques. Pour répondre à ce problème, nous ajoutons les mécanismes nécessaires qui permettent l'application des profils et la capture des extensions sémantiques impliquées par l'utilisation d'un profil. Une implémentation de ces différentes extensions est réalisée sous forme d'un plugin Eclipse dans l'outil de modélisation Papyrus UML. / Model Driven Engineering (MDE) places models at the heart of the software engineering process. MDE helps managing the complexity of software systems and improving the quality of the development process. The Model Driven Architecture (MDA) initiative from the Object Management Group (OMG) defines a framework for building design flows in the context of MDE. MDA relies heavily on formalisms which are normalized by the OMG, such as UML for modeling, QVT for model transformations and so on. This work deals with the execution semantics of the UML language applied to embedded real-time applications. In this context, the OMG has a norm which defines an execution model for a subset of UML called fUML (foundational UML subset). This execution model gives a precise semantics to UML models, which can be used for analyzing models, generating code, or verifying transformations. The goal of this PhD thesis is to define and build an execution engine for UML models of embedded real-time systems, which takes into account the explicit hypothesis made by the designer about the execution semantics at a high level of abstraction, in order to be able to execute models as early as possible in the design flow of a system. To achieve this goal, we have extended the fUML execution model along three important axes with regard to embedded real-time systems: - Concurrency: fUML does not provide any mechanism for handling concurrent activities in its execution engine. We address this issue by introducing an explicit scheduler which allows us to control the execution of concurrent tasks. - Time: fUML does not provide any mean to handle time. By adding a clock to the model of execution, we can take into account the elapsed time as well as temporal constraints on the execution of activities. - Profiles: fUML does not take profiles into account, which makes it difficult to personalize the execution engine with new semantic variants. The execution engine we propose allows the use of UML models with profiles, and interprets these profiles as semantic extensions of the execution model. An implementation of these extensions has been realized as an Eclipse plug-in using the Papyrus UML modeling tool.