As time predictability is critical to hard real-time systems, it is not only necessary to accurately estimate the worst-case execution time (WCET) of the real-time tasks but also desirable to improve either the WCET of the tasks or time predictability of the system, because the real-time tasks with lower WCETs are easy to schedule and more likely to meat their deadlines. As a real-time system is an integration of software and hardware, the optimization can be achieved through two ways: software optimization and time-predictable architectural support. In terms of software optimization, we fi rst propose a loop-based instruction prefetching approach to further improve the WCET comparing with simple prefetching techniques such as Next-N-Line prefetching which can enhance both the average-case performance and the worst-case performance. Our prefetching approach can exploit the program controlow information to intelligently prefetch instructions that are most likely needed. Second, as inter-thread interferences in shared caches can signi cantly a ect the WCET of real-time tasks running on multicore processors, we study three multicore-aware code positioning methods to reduce the inter-core L2 cache interferences between co-running real-time threads. One strategy focuses on decreasing the longest WCET among the co-running threads, and two other methods aim at achieving fairness in terms of the amount or percentage of WCET reduction among co-running threads. In the aspect of time-predictable architectural support, we introduce the concept of architectural time predictability (ATP) to separate timing uncertainty concerns caused by hardware from software, which greatly facilitates the advancement of time-predictable processor design. We also propose a metric called Architectural Time-predictability Factor (ATF) to measure architectural time predictability quantitatively. Furthermore, while cache memories can generally improve average-case performance, they are harmful to time predictability and thus are not desirable for hard real-time and safety-critical systems. In contrast, Scratch-Pad Memories (SPMs) are time predictable, but they may lead to inferior performance. Guided by ATF, we propose and evaluate a variety of hybrid on-chip memory architectures to combine both caches and SPMs intelligently to achieve good time predictability and high performance. Detailed implementation and experimental results discussion are presented in this dissertation.

<p>Real-time systems are systems which must produce a result within a given time frame. A result given outside of this time frame is as useless as not delivering any result at all. It is therefore essential to verify that real-time systems fulfill their timing requirements. A model of the system can facilitate the verification process. This thesis investigates two possible methods for modeling a real-time system with respect to CPU-utilization and latency of the different components in the system. The two methods are evaluated and one method is chosen for implementation.The studied system is the decoder of a WCDMA system which utilizes a real-time operating called system OSEck. The methodology of analyzing the system and different ways of obtaining measurements to base the model upon will be described. The model was implemented using the simulation library VirtualTime, which contains a model of the previously mentioned operating system. Much work was spent acquiring input for the model, since the quality of the model depends largely on the quality of the analysis work. The model created contains two of the studied systems main components.This thesis identifies thorough system knowledge and efficient profiling methods as the key success factors when creating models of real-time systems.</p>

Real-time systems comprise computers that must generate correct results in a timely manner. This involves a wide spectrum of computing systems found in our everyday life ranging from computers in rockets to our mobile phones. The criticality of producing timely results defines the different types of realtime systems. On one hand, we have the so-called hard real-time systems, where failing to meet deadlines may result in a catastrophe. In this thesis we are, however, concerned with firm and soft real-time systems, where missing deadlines is acceptable at the expense of degraded system performance. The usage of firm and soft real-time systems has increased rapidly during the last years, mainly due to the advent of applications in multimedia, telecommunication, and e-commerce. These systems are typically data-intensive, with the data normally spanning from low-level control data, typically acquired from sensors, to high-level management and business data. In contrast to hard real-time systems, the environments in which firm and soft real-time systems operate in are typically open and highly unpredictable. For example, the workload applied on a web server or base station in telecommunication systems varies according to the needs of the users, which is hard to foresee. In this thesis we are concerned with quality of service (QoS) management of data services for firm and soft real-time systems. The approaches and solutions presented aim at providing a general understanding of how the QoS can be guaranteed according to a given specification, even if the workload varies unpredictably. The QoS specification determines the desired QoS during normal system operation, and the worst-case system performance and convergence rate toward the desired setting in the face of transient overloads. Feedback control theory is used to control QoS since little is known about the workload applied on the system. Using feedback control the difference between the measured QoS and the desired QoS is formed and fed into a controller, which computes a change to the operation of the real-time system. Experimental evaluation shows that using feedback control is highly effective in managing QoS such that a given QoS specification is satisfied. This is a key step toward automatic management of intricate systems providing real-time data services.

Real-time systems often use SPM instead of cache, because SPM allows a program¡¦s run time to be more predictable. Real-time system need predictable runtimes, because they must schedule programs to finish within specific deadlines. A deadline should be larger than its program¡¦s worst-case execution time (WCET). Our laboratory is conducting ongoing research into scratchpad memory allocation (SPM) for reducing the WCET of a program. Compared to our previous work, this current thesis improves our memory model, our allocation algorithms, our real-time support, and our measurement benchmarks and platform. Our key accomplishments in this paper are to: 1) add, for the first time in the literature, true WCETmeas analysis to an SPM allocator, 2) to modestly improve the performance of our previous allocator, and 3) to greatly increase the applicability over that allocator, by extending the method to support recursive programs.

Finding the worst-case execution time (WCET) on a hard real-time system is extremely important. Only static WCET analysis can give us an upper bound of WCET which guarantees the deadline, however, industrial practice still relies on measurement-based WCET analysis, even for many hard real-time systems; because static analysis tools are not a mature technology. We use SWEET (SWEdish Execution Time tool) to provide WCET analysis support for the ARM. SWEET is a static WCET analyzer developed by the M&#x00E4;lardalen Real-Time Research Center (MRTC). We modified ARM-GCC to obtain input files in specific format for SWEET: ALF, TCD, and MAP. Besides, for WCET optimization supporting and over-optimizing issue, we modified SWEET to obtain additional worst-case flow path (WCFP) and the second worst-case information. By testing with benchmark files from [1], our modified ARM-GCC can create correct input files for SWEET, and also the modified SWEET can produce additional worst-case information.

Real-time embedded systems (RTESs) have been widely used in modern society. And it is also very common to find them in safety and security critical applications, such as transportation and medical equipment. There are, usually, several constraints imposed on a RTES, for example, timing, resource, energy, and performance, which must be satisfied simultaneously. This makes the design of such systems a difficult problem. More recently, the security of RTESs emerges as a major design concern, as more and more attacks have been reported. However, RTES security, as a parameter to be considered during the design process, has been overlooked in the past. This thesis approaches the design of secure RTESs focusing on aspects that are particularly important in the context of RTES, such as communication confidentiality and side-channel attack resistance. Several techniques are presented in this thesis for designing secure RTESs, including hardware/software co-design techniques for communication confidentiality on distributed platforms, a global framework for secure multi-mode real-time systems, and a scheduling policy for thwarting differential power analysis attacks.  All the proposed solutions have been extensively evaluated in a large amount of experiments, including two real-life case studies, which demonstrate the efficiency of the presented techniques.

High-performance signal processing applications is computational intensive, complex and large amount of data has to be processed at every instance. Now these complex algorithms combined with real-time requirements requires that we perform tasks parallel and this should be done within specified time constraints. Therefore high computational system like multicore system is needed to fulfill these requirements, now problem lies in scheduling these real time tasks in multicore system. In this thesis we have studied and compared the different scheduling algorithms available in multicore platform along with hierarchical memory architecture. We have evaluated the performance by comparing their schedulability using tasks from the HPEC benchmark suite for radar signal processing applications. Apart from the comparison described above, we have proposed a new algorithm based on the PD2 scheduling algorithm which called Hybrid PD2 for hierarchical shared cache multicore platform. We have compared the Hybrid PD2 algorithm along with other scheduling algorithms using four randomly generated task sets.

In a modern industrial system, the requirement on computational capacity has increased dramatically, in order to support a higher number of functionalities, to process a larger amount of data or to make faster and safer run-time decisions. Instead of using a traditional single-core processor where threads can only be executed sequentially, multi-core and many-core processors are gaining more and more attentions nowadays. In a multi-core processor, software programs can be executed in parallel, which can thus boost the computational performance. Many-core processors are specialized multi-core processors with a larger number of cores which are designed to achieve a higher degree of parallel processing. An on-chip communication bus is a central intersection used for data-exchange between cores, memory and I/O in most multi-core processors. As the number of cores increases, more contention can occur on the communication bus which raises a bottleneck of the overall performance. Therefore, in order to reduce contention incurred on the communication bus, a many-core processor typically employs a Network-on-Chip (NoC) to achieve data-exchange. Real-time embedded systems have been widely utilized for decades. In addition to the correctness of functionalities, timeliness is also an important factor in such systems. Violation of specific timing requirements can result in performance degradation or even fatal problems. While executing real-time applications on many-core processors, the timeliness of a NoC, as a communication subsystem, is essential as well. Unfortunately, many real-time system designs over-provision resources to guarantee the fulfillment of timing requirements, which can lead to significant resource waste. For example, analysis of a NoC design yields that the network is already saturated (i.e. accepting more traffic can incur requirement violation), however, in reality the network actually has the capacity to admit more traffic. In this thesis, we target such resource wasting problems related to design and analysis of NoCs that are used in real-time systems. We propose a number of solutions to improve the schedulability of real-time traffic over wormhole-switched NoCs in order to further improve the resource utilization of the whole system. The solutions focus mainly on two aspects: (1) providing more accurate and efficient time analyses; (2) proposing more cost-effective scheduling methods.

Execution time estimation plays an important role in computer system design. It is particularly critical in real-time system design, where to meet a deadline can be as important as to ensure the logical correctness of a program. To accurately estimate the execution time of a program can be extremely challenging, since the execution time of a program varies with inputs, the underlying computer architectures, and run-time dynamics, among other factors. The problem becomes even more challenging as computing systems moving from single core to multi-core platforms, with more hardware resources shared by multiple processing cores. The goal of this research is to investigate the relationship between the execution time of a program and the underlying architecture features (e.g. cache size, associativity, memory latency), as well as its run-time characteristics (e.g. cache miss ratios), and based on which, to estimate its execution time on a multi-core platform based on a regression approach. We developed our test platform based on GEM5, an open-source multi-core cycle-accurate simulation tool set. Our experimental results show clearly the strong relationship of the program execution time to architecture features and run-time characteristics. Moreover, we developed different execution time estimation algorithms using the regression approach for different programs with different software characteristics to improve the estimation accuracy.

UAV (Unmanned Airborne Vehicle) is a source of entertainment and a pleasurable experience, attracting many young people to pursue it as a hobby. With the potential increase in the number of UAVs, the risk of using them for malicious purposes also increases. In addition, birds and UAVs have very similar maneuvers during flights. These UAVs can also carry a significant payload, which can have unintended consequences. Therefore, detecting UAVs near red-zone areas is an important problem. In addition, small UAVs can record video from large distances without being spotted by the naked eye. An appropriate network of sensors may be needed to foresee the arrival of such entities from a safe distance before they pose any danger to the surrounding areas. Despite the growing interest in UAV detection, limited research has been conducted in this area due to a lack of available data for model training. This thesis proposes a novel approach to address this challenge by leveraging experimental data collected in real-time using high-sensitivity sensors instead of relying solely on simulations. This approach allows for improved model accuracy and a better representation of the complex and dynamic environments in which UAVs operate, which are difficult to simulate accurately. The thesis further explores the application of machine learning and sensor fusion algorithms to detect UAVs and distinguish them from other objects, such as birds, in real-time. Specifically, the thesis utilizes YOLOv3 with deep sort and sensor fusion algorithms to achieve accurate UAV detection. In this study, we employed YOLOv3, a deep learning model known for its high efficiency and complexity, to facilitate real-time drone versus bird detection. To further enhance the reliability of the system, we incorporated sensor fusion, leading to a more stable and accurate real-time system, and mitigating the incidence of false detections. Our study indicates that the YOLOv3 model outperformed the state-of-the-art models in terms of both speed and robustness, achieving a high level of confidence with a score above 95%. Moreover, the YOLOv3 model demonstrated a promising capability in real-time drone versus bird detection, which suggests its potential for practical applications