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<p>Developing software for mobile terminals is a challenging task because the actual hardware is </p><p>not available at the beginning of the software development phase. Once a hardware prototype is </p><p>available the software development can continue on that platform. But before that a need for a </p><p>model of the actual hardware is needed, hence some kind of emulator or simulator needs to be the </p><p>developed to give the software developers a head start. The aim of this master thesis is to do a </p><p>market survey of the available simulators for the ARM9E CPU and attached devices in a base- </p><p>band chip and test their flexibility in terms of adding additional devices (both external and on </p><p>chip), and also to implement a simulator using the C++ language. The goal is a modular structure </p><p>for easy addition of certain components such as memory-interfaces, external devices etc. Another </p><p>important part is the profiling of the executed code to instrument the execution in different ways, </p><p>and efficiency to allow fast execution. The conclusion of the market study is that due to the high </p><p>price of these simulators (1.5K€-40k€), we need to design our own simulator. Our simulator </p><p>consists of different blocks; some of them are merely stubbed while others like the memory and </p><p>CPU core are modelled more in detail. The performance of the simulator is around 200 KIPS due </p><p>to the overhead in the debugging functionality. By removing the debugging overhead and </p><p>optimizing the memory handling we could achieve at least 1 MIPS on the ARM execution and 5 </p><p>MIPS on the Thumb execution.</p>

Developing software for mobile terminals is a challenging task because the actual hardware is not available at the beginning of the software development phase. Once a hardware prototype is available the software development can continue on that platform. But before that a need for a model of the actual hardware is needed, hence some kind of emulator or simulator needs to be the developed to give the software developers a head start. The aim of this master thesis is to do a market survey of the available simulators for the ARM9E CPU and attached devices in a base- band chip and test their flexibility in terms of adding additional devices (both external and on chip), and also to implement a simulator using the C++ language. The goal is a modular structure for easy addition of certain components such as memory-interfaces, external devices etc. Another important part is the profiling of the executed code to instrument the execution in different ways, and efficiency to allow fast execution. The conclusion of the market study is that due to the high price of these simulators (1.5K€-40k€), we need to design our own simulator. Our simulator consists of different blocks; some of them are merely stubbed while others like the memory and CPU core are modelled more in detail. The performance of the simulator is around 200 KIPS due to the overhead in the debugging functionality. By removing the debugging overhead and optimizing the memory handling we could achieve at least 1 MIPS on the ARM execution and 5 MIPS on the Thumb execution.

The original intent of this pro ject was to perform real time digital communications between a personal computer (PC) as the transmitter and a digital signal processor (DSP) as the receiver using the audio band analog channel. Although transmitter and receiver were both designed with baseband binary Pulse Amplitude Modulation (PAM), a low data rate and a sampling rate of 8 kilohertz, it was not possible to achieve communication between the two with traditional synchronization algorithms because of large differences in sampling clock frequencies. This thesis explores the theory and results of implementing digital communications between systems with different sampling frequencies. The receiver structure has no a priori knowledge of the transmitter’s sampling rate, although it is assumed to be approximately equal to that of the receiver. Therefore, a receiver structure that can correct this clock frequency offset is developed. Similar sampling frequencies at the transmitter and receiver are assumed in most derivations in the literature. A search of the literature found no cases of a large difference in the sampling frequencies. In general, if the receiver knows the transmitter’s sampling rate, a resampling filter at the receiver converts the signal to one compatible with the transmitters sampling rate. However, here it is assumed that the receiver does not know the transmitter’s exact sampling frequency and must be estimated. The mathematical expressions for the signals in the system are derived. The sampling frequency offset introduces errors in the correct detection of the signal when it is done through traditional synchronization algorithms. Therefore, a receiver structure that corrects the sampling frequency offset based on the interpolation concept is proposed. This structure will be shown to work when the correct sampling frequency ratio is known. Later, an approach to estimate the sampling frequency ratio is explored. A feedback estimator structure is derived from the Maximum Likelihood optimum criteria. A feed forward estimator that assumes the clock frequency of the transmitter and uses a synchronization sequence is explored as well.

<p>A forward error correction technique known as convolutional coding with Viterbi decoding was explored in this final thesis. This Viterbi project is part of the baseband Error control project at electrical engineering department, Linköping University.</p><p>In this project, the basic Viterbi decoder behavior model was built and simulated. The convolutional encoder, puncturing, 3 bit soft decision, BPSK and AWGN channel were implemented in MATLAB code. The BER was tested to evaluate the decoding performance.</p><p>The main issue of this thesis is to implement the RTL level model of Viterbi decoder. With the testing results of behavior model, with minimizing the data path, register size and butterflies in the design, we try to achieve a low silicon cost design. The RTL Viterbi decoder model includes the Branch Metric block, the Add-Compare-Select block, the trace-back block, the decoding block and next state block. With all done, we further understand about the Viterbi decoding algorithm and the DSP implementation methods.</p>

<p>WiMAX provides broadband wireless access and uses OFDM as the underlying modulation technique. In an OFDM based wireless communication system, the channel will distort the transmitted signal and the performance is seriously degraded by synchronization mismatches between the transmitter and receiver. Therefore such systems require extensive digital signal processing of the received signal for retrieval of the transmitted information.</p><p>In this master thesis, parts of an IEEE 802.16d (WiMAX) receiver have been implemented on a programmable baseband processor. The implemented parts constitute baseband algorithms which compensates for the effects from the channel and synchronization errors. The processor has a new innovative architecture with an instruction set optimized for baseband applications.</p><p>This report includes theory behind the baseband algorithms as well as a presentation of how they are implemented on the processor. An impartial evaluation of the processor performance with respect to the algorithms used in the reference model is also presented in the report.</p>

<p>The programming languages that describe hardware circuits are important for circuit </p><p>designers to assist them to design and develop the hardware circuits. </p><p> </p><p>In this master’s project, the Lava hardware description language is used to design and </p><p>develop hardware components for a baseband processing API. Lava is a language </p><p>embedded in the general purpose language Haskell. </p><p> </p><p>The function for checking transmission errors in the baseband processing chain, Cyclic </p><p>Redundancy Check (CRC) is implemented in different ways and tested. </p><p>Linear Feedback Shift Registers (LFSRs) circuits for a particular polynomial generator </p><p>are developed, implemented and simulated by using Lava code to calculate the CRC. </p><p> </p><p>A generalized function of CRC is developed as a circuit generator for any given </p><p>polynomial generator. The circuit is tested by automatic test program.</p>

Efficient programmable baseband processors are important to enable true multi-standard radio platforms as convergence of mobile communication devices and systems requires multi-standard processing devices. The processors do not only need the capability to handle differences in a single standard, often there is a great need to cover several completely different modulation methods such as OFDM and CDMA with the same processing device. Programmability can also be used to quickly adapt to new and updated standards within the ever changing wireless communication industry since a pure ASIC solution will not be flexible enough. ASIC solutions for multi-standard baseband processing are also less area efficient than their programmable counterparts since processing resources cannot be efficiently shared between different operations. However, as baseband processing is computationally demanding, traditional DSP architectures cannot be used due to their limited computing capacity. Instead VLIW- and SIMD-based processors are used to provide sufficient computing capacity for baseband applications. The drawback of VLIW-based DSPs is their low power efficiency due to the wide instructions that need to be fetched every clock cycle and their control-path overhead. On the other hand, pure SIMD-based DSPs lack the possibility to perform different concurrent operations. Since memory access power is the dominating part of the power consumption in a processor, other alternatives should be investigated. In this dissertation a new and unique type of processor architecture has been designed that instead of using the traditional architectures has started from the application requirements with efficiency in mind. The architecture is named ``Single Instruction stream Multiple Tasks'', SIMT in short. The SIMT architecture uses the vector nature of most baseband programs to provide a good trade-off between the flexibility of a VLIW processor and the processing efficiency of a SIMD processor. The contributions of this project are the design and research of key architectural components in the SIMT architecture as well as development of design methodologies. Methodologies for accelerator selection are also presented. Furthermore data dependency control and memory management are studied. Architecture and performance characteristics have also been compared between the SIMT and more traditional processor architectures. A complete system is demonstrated by the BBP2 baseband processor that has been designed using SIMT technology. The SIMT principle has previously been proven in a small scale in silicon in the BBP1 processor implementing a Wireless LAN transceiver. The second demonstrator chip (BBP2) was manufactured early 2007 and implements a full scale system with multiple SIMD clusters and a controller core supporting multiple threads. It includes enough memory to run symbol processing of DVB-H/T, WiMAX, IEEE 802.11a/b/g and WCDMA, and the silicon area is 11 mm2 in a 0.12 um CMOS technology.

The programming languages that describe hardware circuits are important for circuit designers to assist them to design and develop the hardware circuits. In this master’s project, the Lava hardware description language is used to design and develop hardware components for a baseband processing API. Lava is a language embedded in the general purpose language Haskell. The function for checking transmission errors in the baseband processing chain, Cyclic Redundancy Check (CRC) is implemented in different ways and tested. Linear Feedback Shift Registers (LFSRs) circuits for a particular polynomial generator are developed, implemented and simulated by using Lava code to calculate the CRC. A generalized function of CRC is developed as a circuit generator for any given polynomial generator. The circuit is tested by automatic test program.

OFDM (Orthogonal Frequency Division Multiplexing) technology, due to its longer symbol duration that decease the amount of dispersion in time caused by multipath delay spread, has been widely used in many advanced digital communication systems such as DVB (Digital Video Broadcast), WLAN (Wireless Local Area Network), and UWB (Ultra Wide Band). How to realize efficient OFDM systems has been a very important issue for either academic or industry fields in recent years. This thesis aims to explore the VLSI implementation of the OFDM system targeted on its application on the wildly popular IEEE802.11a WLAN systems. An efficient OFDM architecture design involves the algorithm exploration and the tradeoff between the algorithm performance and hardware implementation. Therefore, in this thesis, a Matlab simulation platform for the IEEE802.11a baseband receiver is first built to refine several key synchronization algorithms including frame detection, timing recovery, carrier frequency offset, channel estimation as well as phase tracking under some given channel models. An excellent frame detection and timing recovery method is adopted such that nearly perfect synchronization can be achieved at SNR> 3. Furthermore, area-efficient architecture suitable for VLSI implementation for each synchronization module has also been proposed. In summary, 4 complex multipliers with 388 shift registers are required in our synchronization circuits. These modules are integrated with a core single-path radix-23 IFFT (Inverse Fast Fourier Transform) block to build a highly efficient WLAN baseband.