Esse trabalho relata o estudo sobre a aplicação da tecnologia adaptativa na área de linguagens de programação e códigos, tendo como objetivo a proposição de mecanismos que permitam a escrita de códigos que possam se auto-modificar segundo os conceitos da tecnologia adaptativa. Essa proposta é feita por meio da descrição de uma linguagem de montagem para programação adaptativa e de seu mecanismo de execução. Em adição à linguagem, foi desenvolvido um ambiente de execução baseado em um novo dispositivo adaptativo (autômato de execução adaptativo), com o intuito de evitar certas dificuldades existentes à modificação de código impostas pelos mecanismos de execução. Para poder representar e executar códigos adaptativos, esse dispositivo agrega características de execução de ambientes tradicionais e dos autômatos adaptativos. Essa dissertação apresenta o resultado dessa pesquisa, consolidando os conceitos desenvolvidos por meio de exemplos de funcionamento de códigos adaptativos e considerações sobre a linguagem. / This research studies the application of the Adaptive Technology in the field of programming Language and codes, which objective is the proposition of a mechanism designed to build codes capable of self-modifying in compliance which the concepts of Adaptive Technology. This proposal is formulated by means of the description of an assembly language for adaptive programming and its run-time mechanism. In addition to the language proposal, a run-time mechanism based on a new adaptive device (adaptive execution automata) is conceived. That avoids some difficulties to perform code modification existent in traditional run-time mechanisms. In order to represent and execute the adaptive codes, this device aggregates characteristic of the traditional run-time mechanism and the adaptive automata. The present dissertation describes the results of this study, consolidating the concepts developed by means of examples about the code execution operation and considerations about the language.

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

<p>Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis.</p><p>Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware.</p><p>In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on.</p><p>One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.</p>

Reconfigurable computing is an old concept that during the past couple of decades has become increasingly popular. The concept combines the flexibility of software with the performance of hardware. One important contributing factor to the uprising in popularity is the presence of FPGAs (field-programmable gate arrays), which realize the concept by allowing the hardware to be reconfigured dynamically. The current state of reconfigurable computing is discussed further in the thesis. Debugging is a vital part in the development of a hardware design. It can be done in several ways depending on the situation. The most common way is to perform simulations but in some cases the fault-finding has to be done when the design is implemented in hardware. In this thesis a framework concept is designed that utilizes and evaluates some of the reconfigurable computing ideas. The framework provides debugging possibilities for FPGA designs in a novel way, with a modular system where each module provide means to aid finding a specific fault. The framework is added to an existing design, and offers the user a glimpse into the design behavior and the hardware it runs on. One of the debug modules will be released separately under a free license. It allows the developer to see the contents of the memories in a design without requiring special debugging equipment.

It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, it might cause multiple devices to compete for System Bus that caused bus collision. And then the system performance will be limited on the bandwidth. Based on these shortcomings, this paper proposes an architecture which combines DDRx memory with a reconfigurable FPGA to construct a module with both storage and computing functions called Brain module. Brain module¡¦s instruction set is created through the extension of DDRx memory instruction. We also design the brain module controller and Hardware Management Unit. According to the definition of Software-Hardware Co-communication, the dynamically constructed Hardware Management Unit will create a hardware function call mechanism. We also establish internal data switching mechanism to achieve transmission data between memory and reconfigurable computing internal the controller. Thus, it can reduce the workload of System Bus and integrate hardware and software work. In software structure, we inherit the traditional programming language and integrate program data area and reconfigurable computing data area. Brain module data is accessed through memory mapping I/O. User can implement the software-hardware co-work by integrated programming environment,

Reconfigurable and dynamic computer architecture is an exciting area of research that is rapidly expanding to meet the requirements of compute intense real and non-real time applications in key areas such as cryptography, signal/radar processing and other areas. To meet the demands of such applications, a parallel single-chip heterogeneous Hybrid Data/Command Architecture (HDCA) has been proposed. This single-chip multiprocessor architecture system is reconfigurable at three levels: application, node and processor level. It is currently being developed and experimentally verified via a three phase prototyping process. A first phase prototype with very limited functionality has been developed. This initial prototype was used as a base to make further enhancements to improve functionality and performance resulting in a second phase virtual prototype, which is the subject of this thesis. In the work reported here, major contributions are in further enhancing the functionality of the system by adding additional processors, by making the system reconfigurable at the node level, by enhancing the ability of the system to fork to more than two processes and by designing some more complex real/non-real time applications which make use of and can be used to test and evaluate enhanced and new functionality added to the architecture. A working proof of concept of the architecture is achieved by Hardware Description Language (HDL) based development and use of a Virtual Prototype of the architecture. The Virtual Prototype was used to evaluate the architecture functionality and performance in executing several newly developed example applications. Recommendations are made to further improve the system functionality.

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

Neste trabalho estudou-se diversas arquiteturas de dispositivos FPGAs presentes no mercado, visando a utilização desta tecnologia em arquiteturas de computação reconfigurável. Especificamente foram investigados recursos e técnicas de reconfigurabilidade dinâmica destes dispositivos. A possibilidade de reconfigurar dinamicamente o hardware cria diversas expectativas de superação das arquiteturas de computação tradicional. Surge o conceito de hardware virtual, assim como inúmeras dificuldades em utilizar efetivamente esta tecnologia. Outra característica promissora que a tecnologia FPGA oferece é a possibilidade de realizar upgrades remotos do hardware, sem a necessidade de substituição física de equipamentos ou parte deles. Em adicional, foi implementado um sistema multi-FPGAs com dispositivos reconfiguráveis individualmente de forma local ou remota. Este sistema poderá ser a base para uma arquitetura de computação reconfigurável, sendo ela dinâmica ou não. / In this work it was studied several architectures of FPGAs devices available in the market, seeking the use of this technology in architectures of reconfigurable computing. It was specifically researched resources and techniques of dynamic reconfiguration of these devices. The possibility of reconfigure the hardware dynamically creates countless expectations to overcome the architectures of traditional computing. The concept of virtual hardware emerges, as well as a lot of difficulties in using actually this technology. Another promising characteristic that the technology FPGA offers it is the possibility to accomplishing remote upgrades of the hardware, without the need of physical substitution of equipments or of parts of them. In addition, a system multi-FPGAs was implemented with individually reconfigurable devices in local or remote way. This system can be the base for an architecture of reconfigurable computing, being it dynamics or not.

A computação reconfigurável tem se tornado cada vez mais importante em sistemas computacionais embarcados e de alto desempenho. Ela permite níveis de desempenho próximos aos obtidos com circuitos integrados de aplicação específica (ASIC), enquanto ainda mantém flexibilidade de projeto e implementação. No entanto, para programar eficientemente os dispositivos, é necessária experiência em desenvolvimento e domínio de linguagem de descrição de hardware (HDL), tais como VHDL ou Verilog. As técnicas empregadas na compilação em alto nível (por exemplo, a partir de programas em C) ainda possuem muitos pontos em aberto a serem resolvidos antes que se possa obter resultados eficientes. Muitos esforços em se obter um mapeamento direto de algoritmos em hardware se concentram em loops, uma vez que eles representam as regiões computacionalmente mais intensivas de muitos programas. Uma técnica particularmente útil para isto é a de loop pipelining, a qual geralmente é adaptada de técnicas de software pipelining. A aplicação dessas técnicas está fortemente relacionada ao escalonamento das instruções, o que frequentemente impede o uso otimizado dos recursos presentes nos FPGAs modernos. Esta tese descreve uma abordagem alternativa para o mapeamento direto de loops descritos em uma linguagem de alto nível para FPGAs. Diferentemente de outras abordagens, esta técnica não é proveniente das técnicas de software pipelining. Nas arquiteturas obtidas o controle das operações é distribuído, tornando desnecessária uma máquina de estados finitos para controlar a ordem das operações, o que permitiu a obtenção de implementações eficientes. A especificação de um bloco de hardware é feita por meio de uma linguagem de domínio específico (LALP), especialmente concebida para suportar a aplicação das técnicas. Embora a sintaxe da linguagem lembre C, ela contém certas construções que permitem intervenções do programador para garantir ou relaxar dependências de dados, conforme necessário, e assim otimizar o desempenho do hardware gerado / Reconfigurable computing is becoming increasingly important in embedded and high-performance computing systems. It allows performance levels close to the ones obtained with Application-Specific Integrated circuits (ASIC), while still keeping design and implementation flexibility. However, to efficiently program devices, one needs the expertise of hardware developers in order master hardware description languages (HDL) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Many efforts trying to achieve a direct of algorithms into hardware concentrate on loops since they represent the most computationally intensive regions of many application codes. A particularly useful technique for this purpose is loop pipelining, which is usually adapted from software pipelining techniques. The application of this technique is strongly related to instruction scheduling, whic often prevents an optimized use of the resources present in modern FPGAs. This thesis decribes an alternative approach to direct mapping loops described in high-level labguages onto FPGAs. Different from oyher approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient harware implementations. The specification of a hardware block is done by means of LALP, a domain specific language specially designed to help the application of the techniques. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware

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