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The ability of some configurable logic devices to modify their hardware during operation has long held great potential to increase performance and reduce device cost. However, despite many research projects and a decade of research, the dynamic reconfiguration of Field Programmable Gate Arrays (FPGAs) is still very much an art practiced by few. Previous attempts to automate the many low-level details that complicate Run-Time Reconfigurable (RTR) application development suffer severe limitations. This dissertation describes a comprehensive approach to dynamic hardware development, providing a designer with appropriate models for computation, communication, and reconfiguration integrated with a high-level design environment. In this way, many manual and time consuming tasks associated with partial reconfiguration are hidden, permitting a designer to focus instead on a design's behavior. This design and implementation environment has been validated on a variety of relevant applications, quantifying the effects of high-level design. / Ph. D.

Prior to the availability of massively parallel supercomputers, the implementation of choice for scientific computing problems such as large numerical physical simulations was typically a vector supercomputer. Legacy code still exists optimized for vector supercomputers. Rehosting legacy code often requires a complete re-write of the original code, which is a long and expensive effort. This work provides a framework and approach to utilize reconfigurable computing resources in place of a vector supercomputer towards the implementation of a legacy source code without a large re-hosting effort. The choice of a vector processing model constrains the solution space such that practical solutions to the underlying resource constrained scheduling problem are achieved. Reconfigurable computing resources that implement capabilities characteristic of the application's original target platform are examined. The framework includes the following components: (1) a template for a parameterized, configurable vector processing core, (2) a scheduling and allocation algorithm that employs lessons learned from the mature knowledge base of vector supercomputing, and (3) the design of the VectCore co-processor to provide a low-overhead interface and control method for instances of the architectural template. The implementation approach applies the framework to produce VectCore instances tailored for specific input problems that meet resource constraints. Experimental data shows the VectCore approach results in efficient implementations with favorable performance compared to both general purpose processing and fixed vector architecture alternatives for the majority of the benchmark cases. Half the benchmark cases scale nearly linearly under a fixed time scaling model. The fixed workload scaling is also linear for the same cases until becoming constant for a subset of the benchmarks due to resource contention in the VectCore implementation limiting the maximum achievable parallelism. The architectural template contributed by this work supports established vector performance enhancing techniques such as parallel and chained operations. As the hardware resources are scaled, the VectCore approach scales the amount of parallelism applied in a problem implementation. In end-to-end hardware experiments, the VectCore co-processor overhead is shown to be small (less than 4%) compared to the schedule length. / Ph. D.

As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational problems. Each of these platforms has its own specific advantages and disadvantages, which need to be accounted for during application development. Flexible radio communications has been dominated by Software Defined Radios. However, research in industry and universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers tools such as partial reconfiguration, which is a special modification of the standard tool-flow that supports configuration of the selected partial regions on an FPGA. The AgileHW project improves on the Xilinx tools resource allocation and routing scheme to increase the design agility and productivity. This thesis advances the AgileHW reconfigurable platform so developers can use the newer technology to build enhanced designs. / Master of Science

The focus of this thesis is on specialising the configuration of a field-programmable gate array (FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration of an application has numerous advantages, but due to the overhead introduced by this process, it is only advantageous if the execution time exceeds reconfiguration time. This implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time applications are therefore typically not reconfigured. A method proposed in the literature to ameliorate the overhead from the configuration process is to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating the need for a processor bus by storing the configuration in localised memory. The drawback of this architecture is the limited size of the BRAM, implying only a subset of configurations can be stored. The work presented in this thesis aim to address this size limitation by proposing a specialiser capable of adapting the configuration stored in the BRAM to represent different sets of hardware. This is done by directly manipulating the bits in the configuration using passive hardware. This not only allows the configuration to be specialised practically immediately, but also allows this specialiser to be device independent. By incorporating this specialiser into the BRAM-based architecture, this study sets out to establish that it is possible to reduce the overhead of the reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time applications. Since the composition of the configuration is not publicly available, a method had to be found to parse and analyse the configuration in order to map the configuration space of the device. The approach used was to compare numerous different configurations and mapping the differences. By analysing these differences, it was found that there is a logical relationship between the slice coordinates and the configuration space of the device. The encoding of the lookup tables was also determined from their initialisation parameters. This allows the configuration of any lookup table to be changed by simply changing the corresponding bits in the configuration. Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi figured and its functional density measured. The reason for selecting this specific application is because the multiply-accumulate instruction can be found at the heart of many real-time applications. If the functional density of the reconfigured application is comparable to those of its static equivalent, a strong case can be made for real-time reconfiguration in general. Functional density is an indication of the composite benefits dynamic reconfiguration obtains above its static generic counterpart. Due to the overhead of the reconfiguration process, the functional density of reconfigured applications is traditionally significantly lower than those of static applications. If the functional density of the reconfigured application can rival those of the static equivalent, the overhead from the reconfiguration process becomes negligible. Using this metric, the functional density of the distributed multiply-accumulate was compared for different reconfiguration implementations. It was found that the reconfiguration architecture proposed in this thesis yields a significant improvement over other reconfiguration methods. In fact, the functional density of this method rivalled that of its static equivalent, implying that it is possible to dynamically reconfigure a real-time application. It was also found that the proposed architecture reduces specialisation and reconfiguration time to such an extent that it is possible complete the reconfiguration process within strict time constraints. Even though the proposed method is only capable of reconfiguring the LUTs of a real-time application, this is the first step towards allowing full reconfiguration of applications with dynamic characteristics. The first contribution this thesis makes is a novel method to parse and analyse the configuration of a XilinxR VirtexR -5 FPGA. It also successfully maps the configuration space to the configuration data. Even though this method is applied to a specific device, it is device independent and can easily be applied to any other FPGA. The second contribution comes from using the information obtained from this analysis to design and implement a configuration specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution combines this specialiser with the BRAM-based architecture to allow the reconfiguration of applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

The focus of this thesis is on specialising the configuration of a field-programmable gate array (FPGA) to allow dynamic reconfiguration of real-time applications. The dynamic reconfiguration of an application has numerous advantages, but due to the overhead introduced by this process, it is only advantageous if the execution time exceeds reconfiguration time. This implies that dynamic reconfiguration is more suited to quasi-static applications, and real-time applications are therefore typically not reconfigured. A method proposed in the literature to ameliorate the overhead from the configuration process is to use a block-RAM (BRAM) based, hardware-controlled reconfiguration architecture, eliminating the need for a processor bus by storing the configuration in localised memory. The drawback of this architecture is the limited size of the BRAM, implying only a subset of configurations can be stored. The work presented in this thesis aim to address this size limitation by proposing a specialiser capable of adapting the configuration stored in the BRAM to represent different sets of hardware. This is done by directly manipulating the bits in the configuration using passive hardware. This not only allows the configuration to be specialised practically immediately, but also allows this specialiser to be device independent. By incorporating this specialiser into the BRAM-based architecture, this study sets out to establish that it is possible to reduce the overhead of the reconfiguration process to such an extent that dynamic reconfiguration can be used for real-time applications. Since the composition of the configuration is not publicly available, a method had to be found to parse and analyse the configuration in order to map the configuration space of the device. The approach used was to compare numerous different configurations and mapping the differences. By analysing these differences, it was found that there is a logical relationship between the slice coordinates and the configuration space of the device. The encoding of the lookup tables was also determined from their initialisation parameters. This allows the configuration of any lookup table to be changed by simply changing the corresponding bits in the configuration. Using this proposed reconfiguration architecture, a distributed multiply-accumulate was reconi figured and its functional density measured. The reason for selecting this specific application is because the multiply-accumulate instruction can be found at the heart of many real-time applications. If the functional density of the reconfigured application is comparable to those of its static equivalent, a strong case can be made for real-time reconfiguration in general. Functional density is an indication of the composite benefits dynamic reconfiguration obtains above its static generic counterpart. Due to the overhead of the reconfiguration process, the functional density of reconfigured applications is traditionally significantly lower than those of static applications. If the functional density of the reconfigured application can rival those of the static equivalent, the overhead from the reconfiguration process becomes negligible. Using this metric, the functional density of the distributed multiply-accumulate was compared for different reconfiguration implementations. It was found that the reconfiguration architecture proposed in this thesis yields a significant improvement over other reconfiguration methods. In fact, the functional density of this method rivalled that of its static equivalent, implying that it is possible to dynamically reconfigure a real-time application. It was also found that the proposed architecture reduces specialisation and reconfiguration time to such an extent that it is possible complete the reconfiguration process within strict time constraints. Even though the proposed method is only capable of reconfiguring the LUTs of a real-time application, this is the first step towards allowing full reconfiguration of applications with dynamic characteristics. The first contribution this thesis makes is a novel method to parse and analyse the configuration of a XilinxR VirtexR -5 FPGA. It also successfully maps the configuration space to the configuration data. Even though this method is applied to a specific device, it is device independent and can easily be applied to any other FPGA. The second contribution comes from using the information obtained from this analysis to design and implement a configuration specialiser, capable of adapting lookup tables in real time. Lastly, the third contribution combines this specialiser with the BRAM-based architecture to allow the reconfiguration of applications typically not reconfigured. / PhD (Computer and Electronic Engineering), North-West University, Potchefstroom Campus, 2015

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Over a dozen commercial remote sensing programs are currently under development representing billions of dollars of potential investment. While technological advances have dramatically decreased the cost of building and launching these satellites, the cost and complexity of accessing their data for commercial use are still prohibitively high. This paper describes Reconfigurable Gateway Systems which provide, to a broad spectrum of existing and new data users, affordable telemetry data acquisition, processing and distribution for real-time remotely sensed data at rates up to 300 Mbps. These Gateway Systems are based upon reconfigurable computing, multiprocessing, and process automation technologies to meet a broad range of satellite communications and data processing applications. Their flexible architecture easily accommodates future enhancements for decompression, decryption, digital signal processing and image / SAR data processing.

As arquiteturas multiprocessadas heterogêneas têm como objetivo principal a extração de maior desempenho da execução dos processos, por meio da utilização de núcleos apropriados às suas demandas. No entanto, a extração de maior desempenho é dependente de um mecanismo eficiente de escalonamento, capaz de identificar as demandas dos processos em tempo real e, a partir delas, designar o processador mais adequado, de acordo com seus recursos. Este trabalho tem como objetivo propor e implementar o modelo de um escalonador para arquiteturas multiprocessadas heterogêneas, baseado em software e hardware, aplicado ao sistema operacional Linux e ao processador SPARC Leon3, como prova de conceito. Nesse sentido, foram implementados monitores de desempenho dentro dos processadores, os quais identificam as demandas dos processos em tempo real. Para cada processo, sua demanda é projetada para os demais processadores da arquitetura e em seguida é realizado um balanceamento visando maximizar o desempenho total do sistema, distribuindo os processos entre processadores, de modo a diminuir o tempo total de processamento de todos os processos. O algoritmo de maximização Hungarian, utilizado no balanceamento do escalonador, foi desenvolvido em hardware, proporcionando paralelismo e maior desempenho na execução do algoritmo. O escalonador foi validado por meio da execução paralela de diversos benchmarks, resultando na diminuição dos tempos de execução em relação ao escalonador sem suporte à heterogeneidade / Heterogeneous multiprocessor architectures have as main objective the extraction of higher performance from processes through the use of appropriate cores to their demands. However, the extraction of higher performance is dependent on an efficient scheduling mechanism, able to identify in real-time the demands of processes and to designate the most appropriate processor according to their resources. This work aims at design and implementations of a model of a scheduler for heterogeneous multiprocessor architectures based on software and hardware, applied to the Linux operating system and the SPARC Leon3 processor as proof of concept. In this sense, performance monitors have been implemented within the processors, which in real-time identifies the demands of processes. For each process, its demand is projected for the other processors in the architecture and then it is performed a balancing to maximize the total system performance by distributing processes among processors. The Hungarian maximization algorithm, used in balancing scheduler was developed in hardware, providing greater parallelism and performance in the execution of the algorithm. The scheduler has been validated through the parallel execution of several benchmarks, resulting in decreased execution times compared to the scheduler without the heterogeneity support