Microelectronic wire bonding is a manufacturing process used to electrically connect integrated circuits with circuit boards or other substrates. Conventionally, balls are molten at the end of a Au bonding wire and subsequently bonded on Al metallization of a integrated circuit. However, Pd/Ni metallization has recently been used for its improved mechanical properties. The bondability, bonding mechanism, and reliability of Au ball bonds on Pd are studied in this thesis. The substrates were produced in this project using three different materials. The base material is polished Cu in the shape of a coupon (1.0 cm × 1.0 cm × 0.5 mm). Cu coupons are plated with Ni (1.0 μm) using an electroless process, followed by electrolytic plating of a layer of Pd (0.3 μm), resulting in an arithmetic mean roughness of the surface of 0.08 μm (baseline sample, sample 0). Higher roughness values of 0.2, 0.4, and 0.5 μm are artificially produced by rolling (sample 1), sanding (sample 2), and sandblasting (sample 3), respectively, on the Cu surface before plating Ni and Pd. A 25 μm diameter Au wire is used for bonding on the polished and roughened substrates with a process temperature of T = 220 °C, and it was found that ≈ 4 % to ≈ 18 % less ultrasonic amplitude was required for successful bonding on the roughened substrates compared to the polished substrate. Bondability is measured by shear testing the ball bonds. An average ball bond strength achieved on the polished substrate is 130 MPa. This value is lower on the roughened substrate with the exception of the sandblasted substrate. Long-term thermal aging at 250 °C was performed with ball bonds on samples 0-3 for durations of ≈ 300 h. The reliability of the bonds is characterized by non-destructive contact resistance analysis during aging and destructive cross section analysis after aging. Contact resistance values for the ball bonds range from 1.6 to 3.5 mΩ at 20 °C before aging, and does not correlate with roughness. For the baseline sample, contact resistance of the ball bonds decreases during aging by -6 % (median value), which indicates electrical integrity of the interconnections at high temperature. This decrease possibly is due to interfacial gap filling by Au or Pd diffusion. In contrast, the contact resistance increases for the roughened samples 1-3 and changes are 0.4, 5, and 14 %, respectively (median values). A conclusive explanation for this increase has not yet been found. After 250 h of aging, a TEM analysis showed Au to Pd diffusion in the baseline sample with a diffusion depth of ≈ 0.1 μm Au. No intermetallics, voids, or contamination is found on the interfaces after aging according to nanohardness, SEM, and TEM analyses. No bond lift-offs or electrical opens were found for the aging temperature and durations chosen. No conclusive evidence for the presence of Au-Pd intermetallics or voids is found.

Bulk electric system reliability assessment is an important activity in both vertically integrated and unbundled electric power utilities. The conventional deterministic N-1 criterion normally used in bulk electric system planning does not respond to the probabilistic factors that influence the reliability of the system and is a rigid criterion. New assessment procedures are therefore required that combine the traditional deterministic approach with probabilistic perspectives to provide a responsive planning criterion.<p>This research work introduces the concept of a joint deterministic-probabilistic (D-P) criterion for bulk electric system planning using a previously developed software package designated as MECORE. The D-P concept presented is a deterministic framework that incorporates a probabilistic criterion. This research examines the application of the conventional deterministic N-1, the basic probabilistic and the D-P criteria to two test systems. The studies show that the D-P approach is driven by the accepted deterministic N-1 criterion and influenced by the probabilistic criterion (Pc). The D-P technique adds additional probabilistic risk information to the traditional deterministic N-1 criterion that is useful when making system reinforcement decisions. <p>The research work illustrated in this thesis indicates that the D-P criterion and associated procedures for bulk electric system analysis can be effectively utilized in bulk electric system reliability assessment. The conclusions and the techniques presented in this thesis should prove valuable to those responsible for composite generation and transmission system expansion planning.

A performance model and a reliability-based optimization model for flexible pavements that accounts for the effects of rehabilitation actions are developed. The developed performance model can be effectively implemented in all the applications that require the reliability (performance) of pavements, before and after the rehabilitation actions. The response surface methodology in conjunction with Monte Carlo simulation is used to evaluate pavement fragilities. To provide more flexibility, the parametric regression model that expresses fragilities in terms of decision variables is developed. Developed fragilities are used as performance measures in a reliability-based optimization model. Three decision policies for rehabilitation actions are formulated and evaluated using a genetic algorithm. The multi-objective genetic algorithm is used for obtaining optimal trade-off between performance and cost. To illustrate the developed model, a numerical study is presented. The developed performance model describes well the behavior of flexible pavement before as well as after rehabilitation actions. The sensitivity measures suggest that the reliability of flexible pavements before and after rehabilitation actions can effectively be improved by providing an asphalt layer as thick as possible in the initial design and improving the subgrade stiffness. The importance measures suggest that the asphalt layer modulus at the time of rehabilitation actions represent the principal uncertainty for the performance after rehabilitation actions. Statistical validation of the developed response model shows that the response surface methodology can be efficiently used to describe pavement responses. The results for parametric regression model indicate that the developed regression models are able to express the fragilities in terms of decision variables. Numerical illustration for optimization shows that the cost minimization and reliability maximization formulations can be efficiently used in determining optimal rehabilitation policies. Pareto optimal solutions obtained from multi-objective genetic algorithm can be used to obtain trade-off between cost and performance and avoid possible conflict between two decision policies.

1.Sn/Ag4.0/Cu0.5 solder with better performance by the improved reflow profile. 2.The Sn/Ag2.6/Cu0.6¡BSn/Ag4.0/Cu0.5 with similar reliability test performance.

The influence of grain boundary (GB) on stability of poly-silicon thin film transistor (TFT) have been investigated in this work. The work was supported by the National Science Council of the Republic of China and AUO. We used ac stress and dc stress conditions to stress different TFTs, and investigate the influence of grain boundary by use of electrical analysis. The SLS poly-Si TFT which does contain GB perpendicular to the channel direction owns the higher ability against dc stress and poorer ability against ac stress than the poly-Si TFT which does not contain GB. The physical mechanism for these results has been reasonably deduced by use of TFT device simulation tool (ise-tcad).

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ABSTRACT In package, it¡¦s easy to have defects in the solder joint, for the request of environment protection, lead-free solder research is one of the most important topics now. In soldering, the adhesion, diffusion barrier, and wettability of the interface between UBM and a lead-free solder, and the caused IMC structure that are important elements to influence long-term reliability tests. The thesis is aimed to investigate the combination of pure tin/Al-NiV-Cu UBM/STD Au substrate under reliability tests. The samples are bare dies in which the combination is pure tin/ Al-NiV-Cu UBM and packages of is pure tin/Al-NiV-Cu UBM/STD Au substrate. The goals are to realize the mechanical properties under multiple reflows and long term HTST tests with different temperatures and the operational life. We also uses SEM to observe the growth of IMC and the failure modes that help us to realize the connection between failure modes and IMC. The results of experiment can be concluded as follows. In a bare die, 260¢Jmultiple reflows test causes delamination between IMC and die, but doesn¡¦t affect the mechanical properties of it, and HTST test lowers the bump shear strength of it. In package, multiple reflows test and HTST test lower the mechanical properties significantly, the result also means that the adhesion between bump and die will drop significantly as tests go on. In HTOL test with the conditions of 150¢J and 320mA, the average stable service time of the package is 892 hours, and the average ultimate service time of the package is 1,053 hours, most probable failure site is in R1 joint.

English Abstract In this thesis, we investigate the electrical properties and reliabilities of poly-Si TFTs for system on panel application. Roughly, we divide the thesis into two parts, n-type and p-type TFTs respectively. In n-type TFT, we mainly study degradation characteristics of TFTs under dynamic stress. On the other hand, we focus on special negative bias temperature instability (NBTI) degradation for p-type poly-Si TFTs. Because grain boundary in poly-Si film and serious self-heating effect due to glass substrate, which has a poor thermal conductivity, the electrical properties and reliabilities of poly-Si TFTs become more complicated, compare with metal-oxide-semiconductor field effect transistor (MOSFET). Therefore, in the thesis, we found some strange phenomena never observed in a-Si TFT and MOSFET. In chapter 3, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated at room temperature under dynamic voltage stress, which simulate under high frequency operation as driving devices. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000 second stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150◦C, the ON-current of TFT only decrease to 75 percent of the initial value after 1000 second AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious. In chapter 4, the degradation mechanism of n-channel poly-silicon thin film transistor (poly-Si TFT) has been investigated under dynamic voltage stress, which simulate under low frequency operation as pixel switches. Surprisingly, two totally different degradations of TFTs were observed after dynamic stress. Firstly field-effect mobility and driving current increased during early stress. However, a clear and rapid degradation of field-effect mobility occurred instead during later stress. Additionally, the threshold voltage of stressed TFTs strangely shifted to negative direction in later stress, which was never observed in early stress. Finally, we clarify the degradation mechanisms for early and later stress respectively by varied temperature experiments. In chapter 5, the characteristics of p-type poly-silicon thin film transistor (poly-Si TFT) with dynamic bias stress were investigated. The AC stress is operated with the constant drain voltage (15V) and the varying gate voltage (0V~-15V) to degrade the devices. There are some phenomena which cannot be completely explained by typical NBTI mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could rise channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO2 interface due to the Joule heating. The released hydrogen reacts with SiO2 and causes the fixed charge in the gate oxide. Thus, the degradation of electrical characteristics of device is mainly dominated by the self-heating induced NBTI effect. In chapter 6, we investigate the asymmetric negative bias temperature instability degradation of poly-Si TFTs. Electric measurements of normal and reverse modes were employed to analyze the degradation on Vt, current, leakage current and sub-threshold swing (S.S.). The results indicated that a non-uniform vertical electric field at the poly-Si/SiO2 resulted in asymmetric negative bias temperature instability degradation. The trap generation was a grading distribution from source to drain. Moreover, some energy diagrams were proposed to explain the experimental data. Sequentially, asymmetric TFT degradation resulted from a grading distribution of trap state induced by asymmetric NBTI.