The incorporation of Si1-xGex alloy heterostructures into conventional Si processes has been proposed as a means of improving the operating frequency and overall performance of Si field effect transistors. One parameter expected to benefit from this approach is the hole mobility, which would have important implications for high speed CMOS applications. Measured values of the hole mobility, however, have failed to live up to early expectations, and much ongoing research is directed at understanding whether this is an intrinsic limitation (e.g. due to alloy disorder scattering), or due to imperfections arising in the growth and fabrication process. In this thesis, a detailed theoretical study is presented of the hole mobility in single sub-band Si1-xGex heterostructures.

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Amorphous a-SiNx (:H) films have been prepared by radio-frequency sputtering in an argon-nitrogen-hydrogen atmosphere. Both hydrogenated and non-hydrogenated films were studied along with films prepared by the glow-discharge decomposition of a gaseous mixture of silane and ammonia. Photoemission experiments were performed on the sputtered samples. The position and strength of the core levels were determined, along with the plasma energies as a function of x. A comprehensive study of the number and types of defects present within a-SiN(:H) was undertaken. Films sputtered at room temperature and at 200°C, both with and without hydrogen, were studied along with films prepared by the glow-discharge technique. The results obtained are discussed in the light of existing models. Certain characteristic energies obtainable from optical data have been found for hydrogenated and non-hydrogenated films. These results are then related to other experimental results, in particular those from photoemission measurements. Reflection measurements have been made in the range 0.5eV to 12eV on the sputtered and glow-discharge films. From the reflection measurements e2 spectra were determined by Kramers-Kronig analysis. The dependence of the optical joint density of states with alloying was found from the data. It was found from these measurements that the top of the valence band gradually changes from Si3p states to N 2p states.

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M.Ing. (Electrical And Electronic Engineering) / A need was established for the development of a acoustical sensor in silicon. The acoustical sensor is based on the silicon pressure sensor. This sensor consists of a silicon membrane which is formed from silicon bulk material by means of etching. By transforming the movement of the membrane into a variation of capacitance, it is possible to detect a change in pressure. Signal processing is needed to insure that the : information, received from the sensor, is useable and accurate. The physical aspects of sound was investigated. An important relationship was derived between the intensity of a sound and the pressure associated with it. Because silicon was used in a mechanical environment, the mechanical properties of the material were investigated. A model was developed to simplify the design of the senor. A expression was derived for the movement of the membrane for any uniform load applied to it. The variation in capacitance was given by integrating over the area of the membrane. The condense microphone was used as a example of a design of a acoustical sensor. Arising from the example, the natural frequency of the silicon membrane was looked into. A variety of diaphragms were made to provide for a wide working area. Some of the manufacturingprocesses were individually examincd and changed to comply with the manufacturing of the diaphragms. The important process of etching was thoroughly investigated. An excellent etching agent was found with which accurate micro machining could be done. Using this etching agent, a variety of silicon and poll silicon diaphragms were made. Most of the silicon diaphragms were suceossfully formed. The. poli silicon diaphragms were however deformed because of internal stress which developed during the forming process. A signal processing circuit was developed to perform the task of transforming the variation in capacitance to a variation in voltage. The circuit utilised the current through the capacitor to establish the variation in capacitance. The current was transferred to a voltage by a differencing current amplifier. Further signal processing is done by a analogue multiplier.

Silicon with its mature integration platform has brought electronic circuits to mass-market applications; silicon photonics will most probably follow this evolution. However, there are still many technological challenges to be addressed in order to realize silicon photonics technology. One of the key challenges is building a complete design environment interfaced with standard EDA tools; as in microelectronics, this would enable the creation of photonic libraries and photonic IP blocks. In this study, we focus on developing a physical verification (PV) flow for the silicon photonics technology.There are a number of components from the traditional CMOS IC physical verification world that can be borrowed. All, however, will require some modification due to the distinct nature of photonic circuits. We study the photonic circuit PV requirements, in comparison with those for traditional IC designs. The most significant limitation of current PV tools is to handle non- Manhattan layout designs. We adapt industrial standard PV tools to perform efficient and reliable design rule checking (DRC) that validates non-Manhattan like layout. We also propose methodologies and develop a layout versus schematic (LVS) checking flow specific to the non- Manhattan characteristics and photonic circuit verification requirements. The flow is capable of verifying photonic circuit layout implementation (or even manufactured silicon) with regard to the intended design. The developed flows are demonstrated with Mentor Graphics Pyxis design environment and Calibre® PV tool suit. As generic methodologies, they can also be in principle adopted in other EDA tool environments in order to verify the physical implementation of the photonic designs. Such a PV flow is essential for bringing the silicon photonics technology onto the real CMOS streamline. / La plate-forme d'intégration silicium est arrivée à maturité, et a amené les circuits intégrés électroniques (IC) aux applications du marché de masse ; la photonique sur silicium va suivre probablement cette évolution. Pourtant, il y a encore de nombreux défis technologiques à relever pour réaliser la technologie photonique sur silicium. Parmi les principaux défis, il est essentiel de se concentrer sur la construction d'un environnement de conception complet interfacé avec les outils EDA standards ; comme dans la microélectronique, il permettrait la création de librairies photoniques et des blocs IP photoniques. Dans cette étude, nous nous concentrons sur l’adaptation et le développement du flot de vérification physique (PV, ou « physical verification ») pour la conception photonique sur silicium.Il y a un certain nombre de concepts de PV existant pour le CMOS traditionnel qui peuvent être empruntés. Tous, cependant, nécessiteront quelques modifications en raison de la nature distincte du circuit photonique. Nous étudions les exigences de PV pour les circuits photoniques, en comparaison avec celles de la conception de circuits intégrés traditionnels. La limitation la plus importante des outils de PV actuels est de traiter les layout « non-Manhattan ». Nousadaptons des outils industriels standards pour effectuer un « design rule checking » (DRC) efficace et fiable qui valide les layout non-Manhattan. Nous proposons également des méthodologies et développons un flot « layout versus schematic » (LVS) spécifique aux caractéristiques non-Manhattan et aux exigences de vérification de circuits photoniques. Le flot est capable de vérifier le layout du circuit photonique (ou même le silicium fabriqué du circuit) en ce qui concerne la conception cible. Les flots développés sont démontrées avec les outils de Mentor Graphics – Pyxis (l’environnement de dessin) et Calibre® (les outils de PV). Comme les méthodologies génériques, ils peuvent aussi être en principe adoptés dans d'autres outils EDA afin d'effectuer la vérification de la réalisation de la conception du circuit photonique. Un tel flot de PV est essentiel pour amener la technologie photonique sur silicium sur la ligne de production réelle de CMOS.

Cell patterning platforms support diverse research goals including tissue engineering, the study of cell physiology, and the development of biosensors. Patterning and interfacing with neurons is a particular challenge, being approached via various bioengineering approaches. Such constructs, when optimised, can inform our understanding of neuronal computation and learning, and ultimately aid the development of intelligent neuroprostheses. A fundamental pre-requisite is the ability to dictate the spatial organization and topography of patterned neuronal cells. This thesis details efforts to pattern neurons using photolithographically defined arrays of the polymer parylene-C, printed upon oxidised silicon wafers. Initial work focused on exploring the parylene-C:SiO2 construct as a wide-ranging cell-patterning platform, assessing cell adhesion from both substrate- and cell-centric perspectives. Next, the LUHMES (Lund Human Mesencephalic) cell line was used to explore the potential for construction of interrogatable, topographically-defined neuronal networks. In isolation, LUHMES neurons failed to pattern and did not show any morphological signs of cellular differentiation. However, in the context of a cellular template (the HEK 293 cell line which was found to pattern reliably), LUHMES were able to adhere secondarily on-chip. This co-culture environment promoted morphological differentiation of neurons. As such, HEK 293 cells fulfilled a role analogous to glia, dictating neuronal cell adhesion and generating an environment conducive to neuronal survival. Neurites extended between islands of adherent cell somata. The geometry and configuration of parylene-C influenced the organisation of neurites. With appropriate designs, orthogonal neuronal networks could be created. The dominant guidance cue for neurite growth direction appears to be a diffusible chemotactic agent. HEK 293 cells were later replaced with slower growing human glioma-derived precursors, extracted during tumour debulking surgery. These primary cells patterned accurately on parylene-C and provided a similarly effective, and longer lasting, scaffold for neuronal adhesion.

The dissertation focuses on the analysis of the extended defects present in as-grown and proton bombarded β-SiC (annealed and unannealed) grown by chemical vapour deposition (CVD) on (001) Si. The proton irradiation was done to a dose of 2.8 × 1016 protons/cm2 and the annealing took place at 1300°C and 1600°C for 1hr. The main techniques used for the analysis were transmission electron microscopy (TEM) and high resolution TEM (HRTEM). From the diffraction study of the material the phase of the SiC was confirmed to be the cubic beta phase with the zinc-blende structure. The main defects found in the β- SiC were stacking faults (SFs) with their associated partial dislocations and microtwins. The SFs were uniformly distributed throughout the foil. The SFs were identified as having a fault vector of the type 1/3 <111> with bonding partial dislocations of the type 1/6 <121> by using image simulation. The SFs were also found to be predominantly extrinsic in nature by using HRTEM analysis of SFs viewed edge-on. Also both bright and dar-field images of SFs on inclined planes exhibited symmetrical and complementary fringe contrast images. This is a result of the anomalous absorption ratio of SiC lying between that of Si and diamond. The analysis of the annealed and unannealed irradiated β-SiC yielded no evidence of radiation damage or change in the crystal structure of the β-SiC. This confirmed that β-SiC is a radiation resistant material. The critical proton dose for the creation of small dislocation loops seems to be higher than for other compound semiconductors with the zinc-blende structure.

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