The hydrogen (H2) gas sensing mechanism driving 3C-SiC resistive gas sensors is investigated in this work in which two hypotheses are proposed. One hypothesis involves the surface adsorption of H2 on the sensor surface with the adsorbed molecules influencing the flow of current in a resistive gas sensor, termed the surface adsorption detection mechanism. The second hypothesis includes the transfer of heat from the sensor to the gas, producing a change in the temperature of the device when the heat transfer characteristics of the gas change, termed the thermal detection mechanism. The heat transfer characteristics of the gas are dependent on the thermal conductivity of the gas, a property which is a strong function of gas composition. Thus, the thermal detection mechanism mainly detects changes in the thermal conductivity of a gas or gas mixture.Initial experiments suggested the surface adsorption mechanism as the detection mechanism of resistive 3C-SiC gas sensors. However, these experiments were performed in the absence of device temperature measurements. Recent experiments in which the device temperature was measured with a resistance temperature detector (RTD) in thermal contact with the device strongly support the thermal detection mechanism as being responsible for hydrogen gas detection. Experimental observations show the temperature of the resistive 3C-SiC hydrogen gas sensors changes greatly with changing hydrogen gas composition. For example, a 3C-SiC/SOI resistive sensor biased at 10 Vdc displayed a change in temperature from ~400°C to ~216°C, correlating to a change in current from ~41 mA to ~6mA, upon the introduction of 100% H2. The this 3C-SiC/SOI resistive sensor, this large decrease in temperature caused a large increase in resistance which is detected as a decrease in current. Several different experiments have also been performed to confirm the thermal detection mechanism hypothesis.

The heteroepitaxial growth of cubic silicon carbide (3C-SiC) on silicon (Si) substrates at high growth rates, via a horizontal hot-wall chemical vapor deposition (CVD) reactor, has been achieved. The final growth process was developed in three stages; an initial "baseline" development stage, an optimization stage, and a large area growth stage. In all cases the growth was conducted using a two step, carbonization plus growth, process. During carbonization, the surface of the Si is converted to 3C-SiC, which helps to minimize the stress in the growing crystal. Propane (C3H8) and silane (SiH4), diluted in hydrogen (H2), were used as the carbon and silicon source, respectively. A deposition rate of approximately 10 um/h was established during the baseline process. Once the baseline process proved to be repeatable, optimization of the process began. Through variations in temperature, pressure, and the Si/C ratio, thick 3C-SiC films (up to 22 um thick) and high deposition rates (up to 30 um/h) were obtained. The optimized process was then applied to growth on 50 mm diameter Si(100) wafers. The grown 3C-SiC films were analyzed using a variety of characterization techniques. The thickness of the films was assessed through Fourier Transform infrared (FTIR) spectroscopy, and confirmed by cross-section scanning electron microscopy (SEM). The SEM cross-sections were also used to investigate the 3C-SiC/Si interface. The surface morphology of the films was inspected via Nomarsky interference optical microscopy, atomic force microscopy (AFM), and SEM. The crystalline quality of the films was determined through X-ray diffraction (XRD) and low-temperature photoluminescence (LTPL) analysis. A mercury probe was used to make non-contact CV/IV measurements and determine the film doping.

This dissertation research focused on the growth of 4H-SiC epitaxial layers in low-pressure horizontal hot-wall chemical vapor deposition (CVD) reactors. The goal of the research was to develop a growth process that maximized the growth rate and produced films of smooth morphology. The epitaxial growth of SiC was carried out in two different reactor sizes, a 75 mm reactor and a 200 mm reactor. The maximum repeatable growth rate achieved was 30-32 um/h in the 200 mm reactor using the standard chemistry of hydrogen-propane-silane (H2-C3H8-SiH4) at growth temperatures <̲ 1600 °C, which is the highest growth rate reported to date in a horizontal hot-wall reactor at these temperatures. This growth rate was achieved with a silane flow rate of 30 sccm. The process development and characterization of 4H-SiC epitaxial films grown using the standard chemistry are presented. There are many ways to increase the growth rate, such as changing the pressure, increasing the reactant flow rates, or increasing the temperature. The method of choice for this dissertation work was to first increase the reactant flow rates, i.e. silane flow rate, and then to alter the growth chemistry by using a growth additive. When the silane flow is increased, while maintaining a specific growth temperature, supersaturation of silicon may occur. When this happens, particulates may form and deposit onto the sample surface during growth which degrades the film morphology of the epitaxial layers. In order to overcome this severe limitation in the growth of SiC, hydrogen chloride (HCl) was added to the standard chemistry of H2-C3H8-SiH4 during growth when the SiH4 flow was increased beyond 30 sccm. With the addition of HCl, the Si supersaturation was suppressed and the growth rate was increased from ~32 um/h to ~ 49 um/h by increasing the silane precursor up to 45 sccm, while maintaining the Si/C ratio of the standard chemistry process. The addition of HCl to the standard chemistry for growth of SiC films was pioneering work that has since been duplicated by several research groups.

The mechanical properties of polycrystalline materials are governed by the underlying microstructure. In this context, in this dissertation, the role of grain boundaries on the mechanical response of two technologically important materials namely silicon and silicon carbide are examined. In particular, the dynamics of silicon carbide and silicon symmetric tilt bicrystals under shear load are characterized via molecular dynamics simulations. Cubic silicon carbide bicrystals with low-angle grain boundaries exhibit stick-slip behavior due to athermal climb of edge dislocations along the grain boundary at low temperatures. With increasing temperature, stick-slip becomes less pronounced due to competing dislocation glide, and at high-temperatures, structural disordering of the low-angle grain boundary inhibits stick-slip. In contrast, structural disordering of the high-angle grain boundary is induced under shear even at low temperatures, resulting in a significantly dampened stick-slip behavior. When a single layer graphene sheet is introduced at the grain boundary of the symmetric tilt silicon-carbide bicrystals, the resultant shear response is dictated by the orientation of the graphene sheet. Specifically, when the graphene layer is oriented perpendicular to the gain boundary, stick-slip behavior displayed by the low-angle grain boundaries is inhibited, though both low-angle and high-angle grain boundaries exhibit displacement along crystallographic planes parallel with the applied shear direction. On the other hand, when the graphene sheet is parallel to the grain boundary, shear deformation at the grain boundary for both low-angle and high-angle bicrystals is diminished. In silicon bicrystals, high-angle grain boundaries demonstrate coupled motion, characterized by an additional normal motion of the grain boundary. Interestingly, this phenomenon was observed previously in metallic materials. Further, the grain boundary coupling factor, which is ratio of the grain boundary normal velocity to the grain translation velocity, matches the predicted geometric value. The underlying atomic scale mechanisms that govern the grain boundary coupled motion consists of concerted rotations of silicon tetrahedra within the grain boundary. For low-angle grain boundaries in silicon, the activation of dislocation glide along the predicted slip-plane takes precedence and no grain boundary coupling is observed. This behavior is similar to that of silicon carbide seen at high-temperatures but for silicon it occurs for a large temperature window.

Graphene is widely considered to be a promising candidate for a new generation of electronics, but there are many outstanding fundamental issues that need to be addressed before this promise can be realized. This thesis focuses on the production and properties of graphene grown epitaxially on the carbon terminated face (C-face) of hexagonal silicon carbide leading to the construction of a novel graphene transistor structure. C-face epitaxial graphene multilayers are unique due to their rotational stacking that causes the individual layers to be electronically decoupled from each other. Well-formed C-face epitaxial graphene single layers have exceptionally high mobilities (exceeding 10,000 cm^2/Vs), which are significantly greater than those of Si-face graphene monolayers. This thesis investigates the growth and properties of C-face single layer graphene. A field effect transistor based on single layer graphene was fabricated and characterized for the first time. Aluminum oxide or boron nitride was used for the gate dielectric. Additionally, an all graphene/SiC Schottky barrier transistor on the C-face of SiC composed of 2DEG in SiC/Si2O3 interface and multilayer graphene contacts was demonstrated. A multiple growth scheme was adopted to achieve this unique structure.

DC to DC step-down applications with high input voltage and high voltage conversion ratio operational requirements, such as photovoltaic battery chargers, are subject to high conduction losses, high switching losses and substantial reverse-recovery losses when minority carrier principle diodes are used. The recent introduction of silicon carbide diodes with high breakdown voltages has made possible the elimination of reverse-recovery losses at high voltage levels and as such has sparked interest in their use due to the potential efficiency improvements. This report presents the results of a comprehensive analysis on the use of silicon carbide diodes and their counterparts, ultrafast silicon diodes, in conventional buck converters and isolated current-fed buck converters in high input voltage and high voltage conversion ratio step-down applications. The analysis illustrates both theoretically, with the use of steady-state average models, and experimentally the substantial efficiency benefits of the use of reverse-recovery free silicon carbide diodes in the conventional buck converter and the small but significant improvement in the efficiency of the isolated current-fed buck converter. The improvements of the conventional buck converter paired with silicon carbide diodes are shown to be significant enough to grant the variant the most efficient position for power levels below 1 kW. In addition, the four variants are categorized based on their cost and performance; therefore, providing engineers with a convenient guide to aid their selection of the appropriate converter depending on the operational requirements.

The purpose of this work is to explore a method that combines both top-down and bottom-up elements to fabricate electronic devices made from graphene, a single sheet of carbon atoms related to carbon nanotubes and graphite. This material has garnered interest in the semiconductor industry for many reasons, including its potential for ballistic conduction, natural ambipolar (both n- and p-type) carrier transport, and impermeability to nearly all elements. However, its lack of a band gap, and a lack of viable options for creating one in the material, suggests a limited future as a silicon replacement material. A solution to this problem is presented that uses a recently-reported technique of creating pre-patterned graphene features from the thermal decomposition of specially-structured silicon carbide (SiC) surfaces. We employ a combination of direct band structure measurements and electrical results to suggest that a semiconducting bent graphene nanostructure exists in this structured SiC system, creating a possible route toward a broad class of future graphene electronics.

Densification behaviour and mechanical properties (hardness, fracture toughness and flexural strength) of the SiC-TiC composite system were studied. Pressureless sintering experiments were conducted on samples containing 0 to 30 vol % TiC created through an in-situ reaction between TiO2 and C: TiO2 + 3C -> TiC + 2CO. Sintering of the compacts was carried out in the presence of Al2O3 and Y2O3 sintering additives which promoted densification at sintering temperatures ranging from 1825 to 1925°C. It was determined that the presence of synthesized TiC particles served to effectively toughen the composite through crack deflection, impedance and bridging. An increase in fracture strength and hardness was also observed. Densities in excess of 98 % theoretical density were achieved depending on the sintering conditions and volume fraction of TiC phase. The SiC grain size and morphology was analyzed as a function of TiC volume fraction. The presence of TiC particles in the SiC matrix inhibited the exaggerated grain growth of the SiC grains and activated additional toughening mechanisms. The SiC grains were found to be roughly equiaxed with very fine TiC particles preventing significant elongation. The optimal sintering conditions for room temperature mechanical properties required slow heating through the reaction zone (1300 to 1520°C) followed by a 1 h dwell at 1885°C. At this temperature, the maximum flexural strength of 566 MPa was measured in samples containing 5 vol % TiC. Conversely, a maximum fracture toughness of 5.7 MPa·m0.5 was measured in samples containing 10 vol % TiC sintered at 1900°C. The hardness was shown to increase very little, from ~19.8 GPa in the monolithic SiC samples to 20.1 GPa in samples containing 5 vol % TiC. A theoretical analysis was conducted to model the effect of porosity and grain morphology on the mechanical properties of the SiC matrix and was experimentally verified. / Thesis (Master, Mechanical and Materials Engineering) -- Queen's University, 2010-09-21 15:20:02.797

A low-temperature (<300°C) method to fabricate electrostatically actuated microelectromechanical (MEM) clamped-clamped beam resonators has been developed. It utilizes an amorphous silicon carbide (SiC) structural layer and a thin polyimide spacer. The resonator beam is constructed by DC sputtering a tri-layer composite of low-stress SiC and aluminum over the thin polyimide sacrificial layer, and is then released using a microwave O 2 plasma etch. Deposition parameters have been optimized to yield low-stress films (<50MPa), in order to minimize the chance of stress-induced buckling or fracture in both the SiC and aluminum. Characterization of the deposited SiC was performed using several different techniques including scanning electron microscopy, EDX and XRD. / Several different clamped-clamped beam resonator designs were successfully fabricated and tested using a custom built vacuum system, with measured frequencies ranging from 5MHz to 25MHz. A novel thermal tuning method is also demonstrated, using integrated heaters directly on the resonant structure to exploit the temperature dependence of the Young's modulus and thermally induced stresses.

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.