Currently, the bulk of applications of Formal Concept Analysis (FCA) in software engineering have focussed on software maintenance and re-engineering. In this thesis we broaden the approach by applying FCA to a number of early-phase activities within the software engineering life-cycle. With respect to the requirements engineering phase, a case study is presented comparing two class hierarchies that model aspects of a mass-transit railway ticketing system. The first hierarchy was produced for an existing Object-Z specification of the system while the second was derived using FCA. Contrasting the two hierarchies revealed that they were essentially the same, however, the differences highlighted specification artefacts in the existing hierarchy. With respect to the design phase, the thesis discusses the use of FCA for the navigation and visualisation of Formal Specifications written in Z. In response to the continued call for formal methods tool support, we implement and explore a prototype specification browser that exploits the abstractions afforded by FCA. The research hypothesis is an integrated architecture for navigating formal specifications using FCA. This architecture is realised using ZML and ToscanaJ to produce a practical research tool. The thesis also includes the first broad survey of FCA in the domain of software engineering and an FCA-based methodology for surveying academic literature in general.

Currently, the bulk of applications of Formal Concept Analysis (FCA) in software engineering have focussed on software maintenance and re-engineering. In this thesis we broaden the approach by applying FCA to a number of early-phase activities within the software engineering life-cycle. With respect to the requirements engineering phase, a case study is presented comparing two class hierarchies that model aspects of a mass-transit railway ticketing system. The first hierarchy was produced for an existing Object-Z specification of the system while the second was derived using FCA. Contrasting the two hierarchies revealed that they were essentially the same, however, the differences highlighted specification artefacts in the existing hierarchy. With respect to the design phase, the thesis discusses the use of FCA for the navigation and visualisation of Formal Specifications written in Z. In response to the continued call for formal methods tool support, we implement and explore a prototype specification browser that exploits the abstractions afforded by FCA. The research hypothesis is an integrated architecture for navigating formal specifications using FCA. This architecture is realised using ZML and ToscanaJ to produce a practical research tool. The thesis also includes the first broad survey of FCA in the domain of software engineering and an FCA-based methodology for surveying academic literature in general.

Currently, the bulk of applications of Formal Concept Analysis (FCA) in software engineering have focussed on software maintenance and re-engineering. In this thesis we broaden the approach by applying FCA to a number of early-phase activities within the software engineering life-cycle. With respect to the requirements engineering phase, a case study is presented comparing two class hierarchies that model aspects of a mass-transit railway ticketing system. The first hierarchy was produced for an existing Object-Z specification of the system while the second was derived using FCA. Contrasting the two hierarchies revealed that they were essentially the same, however, the differences highlighted specification artefacts in the existing hierarchy. With respect to the design phase, the thesis discusses the use of FCA for the navigation and visualisation of Formal Specifications written in Z. In response to the continued call for formal methods tool support, we implement and explore a prototype specification browser that exploits the abstractions afforded by FCA. The research hypothesis is an integrated architecture for navigating formal specifications using FCA. This architecture is realised using ZML and ToscanaJ to produce a practical research tool. The thesis also includes the first broad survey of FCA in the domain of software engineering and an FCA-based methodology for surveying academic literature in general.

Currently, the bulk of applications of Formal Concept Analysis (FCA) in software engineering have focussed on software maintenance and re-engineering. In this thesis we broaden the approach by applying FCA to a number of early-phase activities within the software engineering life-cycle. With respect to the requirements engineering phase, a case study is presented comparing two class hierarchies that model aspects of a mass-transit railway ticketing system. The first hierarchy was produced for an existing Object-Z specification of the system while the second was derived using FCA. Contrasting the two hierarchies revealed that they were essentially the same, however, the differences highlighted specification artefacts in the existing hierarchy. With respect to the design phase, the thesis discusses the use of FCA for the navigation and visualisation of Formal Specifications written in Z. In response to the continued call for formal methods tool support, we implement and explore a prototype specification browser that exploits the abstractions afforded by FCA. The research hypothesis is an integrated architecture for navigating formal specifications using FCA. This architecture is realised using ZML and ToscanaJ to produce a practical research tool. The thesis also includes the first broad survey of FCA in the domain of software engineering and an FCA-based methodology for surveying academic literature in general.

Diss. Stockholm : Handelshögskolan, 2002.

This thesis describes the design and deployment of netLab, a self-contained lab environment suitable for use in an upper level networking course. NetLab does not require special hardware, special permissions, kernel modifications, or multiple computers. The laboratory was designed to emphasize hands-on programming over device configuration or performance analysis. NetLab uses network engineering projects to motivate software engineering principles. The main projects are linkLab and routerLab, the implementations of a layer-2 network protocol and a layer-3 routing algorithm simulation. Both projects use a physical-layer emulator providing controllable impairment for thorough testing. The lab has been shown to be capable of expansion to accommodate different protocols. NetLab is a success in that students consistently found netLab to be challenging and exciting, and all ranks of students advanced their skills.

The gravity model for international trade is one of the most successful empirical models in trade literature. There is a long tradition to log-linearise the multiplicative model and to estimate the parameters of interest by least squares. But this practice is inappropriate for several reasons. First of all, bilateral trade flows are frequently zero and disregarding countries that do not trade with each other produces biased results. Second, log-linearisation in the presence of heteroscedasticity leads to inconsistent estimates in general. In recent years, the Poisson gravity model along with pseudo maximum likelihood estimation methods have become popular as a way of dealing with such econometric issues as arise when dealing with origin-destination flows. But the standard Poisson model specification is vulnerable to problems of overdispersion and excess zero flows. To overcome these problems, this paper presents zero-inflated extensions of the Poisson and negative binomial specifications as viable alternatives to both the log-linear and the standard Poisson specifications of the gravity model. The performance of the alternative model specifications is assessed on a real world example, where more than half of country-level trade flows are zero. (authors' abstract) / Series: Working Papers in Regional Science

Made available in DSpace on 2014-12-17T15:47:51Z (GMT). No. of bitstreams: 1 FernandaMS_DISSERT_cad.pdf: 1351543 bytes, checksum: 27a89b596f5bafb661e158d68cfc729c (MD5) Previous issue date: 2010-03-29 / With the increasing complexity of software systems, there is also an increased concern about its faults. These faults can cause financial losses and even loss of life. Therefore, we propose in this paper the minimization of faults in software by using formally specified tests. The combination of testing and formal specifications is gaining strength in searches mainly through the MBT (Model-Based Testing). The development of software from formal specifications, when the whole process of refinement is done rigorously, ensures that what is specified in the application will be implemented. Thus, the implementation generated from these specifications would accurately depict what was specified. But not always the specification is refined to the level of implementation and code generation, and in these cases the tests generated from the specification tend to find fault. Additionally, the generation of so-called "invalid tests", ie tests that exercise the application scenarios that were not addressed in the specification, complements more significantly the formal development process. Therefore, this paper proposes a method for generating tests from B formal specifications. This method was structured in pseudo-code. The method is based on the systematization of the techniques of black box testing of boundary value analysis, equivalence partitioning, as well as the technique of orthogonal pairs. The method was applied to a B specification and B test machines that generate test cases independent of implementation language were generated. Aiming to validate the method, test cases were transformed manually in JUnit test cases and the application, created from the B specification and developed in Java, was tested. Faults were found with the execution of the JUnit test cases / Com o crescente aumento da complexidade dos sistemas de software, h? tamb?m um aumento na preocupa??o com suas falhas. Essas falhas podem causar preju?zos financeiros e at? preju?zos de vida. Sendo assim, propomos neste trabalho a minimiza??o de falhas atrav?s de testes em softwares especificados formalmente. A conjun??o de testes e especifica??es formais vem ganhando for?a na academia principalmente atrav?s dos TBM (Testes Baseados em Modelos). O desenvolvimento de software a partir de especifica??es formais, quando todo o processo de refinamento ? feito rigorosamente, garante que o que est? especificado ser? implementado na aplica??o. Sendo assim, a implementa??o gerada a partir destas especifica??es iria retratar fielmente o que estaria especificado. Mas nem sempre a especifica??o ? refinada at? o n?vel de implementa??o e gera??o de c?digo, e nesses casos os testes gerados a partir da especifica??o tendem a encontrar falhas. Adicionalmente, a gera??o dos chamados testes inv?lidos , ou seja, testes que exercitem cen?rios da aplica??o que n?o foram tratados na especifica??o, complementa mais significativamente o processo de desenvolvimento formal. Sendo assim, neste trabalho ? proposto um m?todo para gera??o de testes a partir de especifica??es formais B. Este m?todo foi estruturado em pseudo-c?digo. O m?todo se baseia na sistematiza??o das t?cnicas de testes caixa preta da an?lise do valor limite, particionamento de equival?ncia, bem como da t?cnica dos pares ortogonais. O m?todo foi aplicado em uma especifica??o B e foram geradas m?quinas B de teste que geram casos de teste independentes de linguagem de implementa??o. Com o intuito de valida??o do m?todo, os casos de teste foram transformados manualmente em casos de teste do JUnit e a aplica??o, criada a partir da especifica??o B, e desenvolvida em Java foi testada. Foram encontradas falhas com a execu??o dos casos de teste JUnit

Made available in DSpace on 2014-12-17T15:48:00Z (GMT). No. of bitstreams: 1 SimoneOS_DISSERT_capa_ate_pag44.pdf: 4276014 bytes, checksum: c178262769ab9981c0bbfc10faf1c633 (MD5) Previous issue date: 2012-02-10 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / The development of smart card applications requires a high level of reliability. Formal methods provide means for this reliability to be achieved. The BSmart method and tool contribute to the development of smart card applications with the support of the B method, generating Java Card code from B specifications. For the development with BSmart to be effectively rigorous without overloading the user it is important to have a library of reusable components built in B. The goal of KitSmart is to provide this support. A first research about the composition of this library was a graduation work from Universidade Federal do Rio Grande do Norte, made by Thiago Dutra in 2006. This first version of the kit resulted in a specification of Java Card primitive types byte, short and boolean in B and the creation of reusable components for application development. This work provides an improvement of KitSmart with the addition of API Java Card specification made in B and a guide for the creation of new components. The API Java Card in B, besides being available to be used for development of applications, is also useful as a documentation of each API class. The reusable components correspond to modules to manipulate specific structures, such as date and time. These structures are not available for B or Java Card. These components for Java Card are generated from specifications formally verified in B. The guide contains quick reference on how to specify some structures and how some situations were adapted from object-orientation to the B Method. This work was evaluated through a case study made through the BSmart tool, that makes use of the KitSmart library. In this case study, it is possible to see the contribution of the components in a B specification. This kit should be useful for B method users and Java Card application developers / O desenvolvimento de aplica??es para smart cards requer um alto grau de confiabilidade. M?todos formais fornecem meios para que esta confiabilidade seja alcan?ada. O m?todo e a ferramenta BSmart fornecem uma contribui??o para que o desenvolvimento para smart cards seja feito com o aux?lio do m?todo formal B, gerando c?digo Java Card a partir de especifica??es B. Para que o desenvolvimento com o BSmart seja efetivamente rigoroso sem sobrecarregar o usu?rio do m?todo ? importante que haja uma biblioteca de componentes reutiliz?veis feitos em B. O KitSmart tem como objetivo prover esse aux?lio. Um primeiro estudo sobre a composi??o dessa biblioteca foi tema de uma monografia de gradua??o do curso de Bacharelado em Ci?ncia da Computa??o da Universidade Federal do Rio Grande do Norte, feita por Thiago Dutra em 2006. Esta primeira vers?o do kit resultou na especifica??o dos tipos primitivos permitidos em Java Card (byte, short e boolean) em B e a cria??o de componentes reutiliz?veis para o desenvolvimento de aplica??es. Esta disserta??o prov? o aperfei?oamento do KitSmart com o acr?scimo da especifica??o da API Java Card em B, e um guia para o desenvolvimento de novos componentes. A API Java Card especificada em B, al?m de estar dispon?vel para ser usada no desenvolvimento de projetos, serve como documenta??o ao especificar restri??es de uso para cada classe da API. Os componentes reutiliz?veis correspondem a m?dulos para manipula??o de estruturas espec?ficas, como data e hora, por exemplo. Estes tipos de estruturas n?o est?o dispon?veis em B ou Java Card. Os componentes reutiliz?veis para Java Card s?o gerados a partir das especifica??es verificadas formalmente em B. O guia cont?m informa??es de consulta r?pida para especifica??o de diversas estruturas e como algumas situa??es foram contornadas para adaptar a orienta??o a objetos ao M?todo B. Este trabalho foi avaliado atrav?s de um estudo de caso feito com a ferramenta BSmart que faz uso da biblioteca KitSmart. Neste estudo de caso, ? poss?vel ver a contribui??o dos componentes em uma especifica??o B. Este kit dever? ser ?til tanto para usu?rios do m?todo B como para desenvolvedores de aplica??es Java Card em geral

Les architectures des systèmes sur puce (System-on-Chip, SoC) actuelles intègrent de nombreux composants différents tels que les processeurs, les accélérateurs, les mémoires et les blocs d'entrée/sortie, certains pouvant contenir des caches. Vu que l'effort de validation basée sur la simulation, actuellement utilisée dans l'industrie, croît de façon exponentielle avec la complexité des SoCs, nous nous intéressons à des techniques de vérification formelle. Nous utilisons la boîte à outils CADP pour développer et valider un modèle formel d'un SoC générique conforme à la spécification AMBA 4 ACE récemment proposée par ARM dans le but de mettre en œuvre la cohérence de cache au niveau système. Nous utilisons une spécification orientée contraintes pour modéliser les exigences générales de cette spécification. Les propriétés du système sont vérifié à la fois sur le modèle avec contraintes et le modèle sans contraintes pour détecter les cas intéressants pour la cohérence de cache. La paramétrisation du modèle proposé a permis de produire l'ensemble complet des contre-exemples qui ne satisfont pas une certaine propriété dans le modèle non contraint. Notre approche améliore les techniques industrielles de vérification basées sur la simulation en deux aspects. D'une part, nous suggérons l'utilisation du modèle formel pour évaluer la bonne construction d'une unité de vérification d'interface. D'autre part, dans l'objectif de générer des cas de test semi-dirigés intelligents à partir des propriétés de logique temporelle, nous proposons une approche en deux étapes. La première étape consiste à générer des cas de tests abstraits au niveau système en utilisant des outils de test basé sur modèle de la boîte à outils CADP. La seconde étape consiste à affiner ces tests en cas de tests concrets au niveau de l'interface qui peuvent être exécutés en RTL grâce aux services d'un outil commercial de génération de tests dirigés par les mesures de couverture. Nous avons constaté que notre approche participe dans la transition entre la vérification du niveau interface, classiquement pratiquée dans l'industrie du matériel, et la vérification au niveau système. Notre approche facilite aussi la validation des propriétés globales du système, et permet une détection précoce des bugs, tant dans le SoC que dans les bancs de test commerciales. / State-of-the-art System-on-Chip (SoC) architectures integrate many different components, such as processors, accelerators, memories, and I/O blocks. Some of those components, but not all, may have caches. Because the effort of validation with simulation-based techniques, currently used in industry, grows exponentially with the complexity of the SoC, this thesis investigates the use of formal verification techniques in this context. More precisely, we use the CADP toolbox to develop and validate a generic formal model of a heterogeneous cache-coherent SoC compliant with the recent AMBA 4 ACE specification proposed by ARM. We use a constraint-oriented specification style to model the general requirements of the specification. We verify system properties on both the constrained and unconstrained model to detect the cache coherency corner cases. We take advantage of the parametrization of the proposed model to produce a comprehensive set of counterexamples of non-satisfied properties in the unconstrained model. The results of formal verification are then used to improve the industrial simulation-based verification techniques in two aspects. On the one hand, we suggest using the formal model to assess the sanity of an interface verification unit. On the other hand, in order to generate clever semi-directed test cases from temporal logic properties, we propose a two-step approach. One step consists in generating system-level abstract test cases using model-based testing tools of the CADP toolbox. The other step consists in refining those tests into interface-level concrete test cases that can be executed at RTL level with a commercial Coverage-Directed Test Generation tool. We found that our approach helps in the transition between interface-level and system-level verification, facilitates the validation of system-level properties, and enables early detection of bugs in both the SoC and the commercial test-bench.