"Recently, there has been some good interest in the field of Dynamic Materials, also referred to as Spatio-Temporal Composites. These materials have been theoretically attributed to show ability to switch their electromagnetic properties in time, as contrast to the spatial variations shown by regular materials of non-dynamic nature, existing naturally. Though there is no exhibition of dynamic material in nature yet, there are suggestions for its synthesis. This paper follows the idea of using standard lossless transmission line model approximating a material substance. Such a material though not truly homogeneous, could be made to vary its properties in time. The aim of this work is to test this idea for its functional efficiency in comparison to analytical results obtained from earlier works on the subject. We make use of Spice simulation for this. An important aspect of this work is to facilitate the dynamic operations in a static environment. Almost all the simulators available today like Spice, ADS, etc intrinsically provide no ability for parameter variations in time. Nonetheless, we make use of certain popular tricks to implement circuits imitating the dynamic circuit components we need. Such implementations are separately tested to demonstrate their success in providing us with the dynamic environment we desire. Finally, within the limitations of the computing capabilities, we could successfully show an agreement between the results obtained and the existing theory. "

This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency.A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice.The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison.Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area. The LPFF presented D-to-Q delays of 60% to 69% longer than the delays of the TGFF and 9% to 11% longer than the delays of the TGCGFF. The LPFF cells require an area that is 15% to 34% larger than the TGFF cells and 6% to 17% larger than the TGCGFF cells.

abstract: Great advances have been made in the construction of photovoltaic (PV) cells and modules, but array level management remains much the same as it has been in previous decades. Conventionally, the PV array is connected in a fixed topology which is not always appropriate in the presence of faults in the array, and varying weather conditions. With the introduction of smarter inverters and solar modules, the data obtained from the photovoltaic array can be used to dynamically modify the array topology and improve the array power output. This is beneficial especially when module mismatches such as shading, soiling and aging occur in the photovoltaic array. This research focuses on the topology optimization of PV arrays under shading conditions using measurements obtained from a PV array set-up. A scheme known as topology reconfiguration method is proposed to find the optimal array topology for a given weather condition and faulty module information. Various topologies such as the series-parallel (SP), the total cross-tied (TCT), the bridge link (BL) and their bypassed versions are considered. The topology reconfiguration method compares the efficiencies of the topologies, evaluates the percentage gain in the generated power that would be obtained by reconfiguration of the array and other factors to find the optimal topology. This method is employed for various possible shading patterns to predict the best topology. The results demonstrate the benefit of having an electrically reconfigurable array topology. The effects of irradiance and shading on the array performance are also studied. The simulations are carried out using a SPICE simulator. The simulation results are validated with the experimental data provided by the PACECO Company. / Dissertation/Thesis / M.S. Electrical Engineering 2011

L'intégration 3DVLSI, également connue sous le nom d'intégration monolithique ou séquentielle, est présentée et évaluée dans cette thèse comme une alternative à la réduction du nœud technologique des circuits logiques CMOS. L’avantage principal de cette technologie par rapport à l'intégration parallèle 3D, déjà existante, est l'alignement précis entre les niveaux, ce qui permet des contacts 3D réduits et plus proches. Un autre avantage, extrêmement favorable à l’approche 3DVLSI, est l’amélioration du placement et du routage par rapport aux circuits planaires, notamment parce qu’elle permet des interconnexions plus courtes et qu’elle offre a un degré de liberté supplémentaire dans la direction Z pour la conception. Par exemple, les fils les plus longs dans les circuits planaires peuvent ainsi être réduits grâce aux contacts 3DCO, en diminuant les éléments parasites d'interconnexion. Il est ainsi possible d’augmenter la vitesse du circuit et de réduire la puissance électrique. Dans ce contexte, la thèse a été divisée en deux parties. La première partie traite de l’évaluation de la Consommation, des Performances et de la Surface (CPS) et donne des recommandations pour la conception des circuits 3D. La deuxième partie traite la variabilité des circuits 3D en utilisant un modèle statistique unifié, et en proposant une approche pour la variabilité des circuits multi-niveaux. / 3DVLSI integration, also known as monolithic or sequential integration is presented and evaluated in this thesis as a potential contender to continue the scaling for CMOS logic circuits. The main advantage of this technology compared to the already existing 3D parallel integration is its high alignment among tiers, enabling small size and pitch with the inter-tier contacts (3DCO). Another great 3DVLSI feature is its improved capability to place and route circuits, compared to the planar approach: the interconnections can be shorter as the design has an additional degree of freedom in the Z direction. For instance, long wires in planar circuits can cut thanks to 3DCO contacts, lowering the interconnection parasitic elements and speeding up the circuit as well as reducing the power. In this framework, the thesis has been divided into two parts: the first part is dedicated to the evaluation of Performance, Power and Area (PPA) of 3D circuits and gives design guidelines. The second part treats the variability in 3D circuits by using a 3D unified statistical model and propose an approach for the multi-tier variability.