Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its small cell size, voltage and process compatibility with CMOS and nano-second read/write speeds. It exhibits high density (3-4x of SRAM), non-volatility and process scalability and hence is widely being considered as a viable alternative for SRAM in last-level caches. As the design and fabrication process matures for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models in STT-MRAM under both parametric variations as well as resistive defects (opens and shorts). Sensitivity of read, write and retention to process parameter variations such as lithographic and material variations are studied. In addition, defects (both intra-cell and inter-cell) and the corresponding fault models have been studied and data patterns which excite these faults are explored.

As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed.

As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizing the overhead of power consumption, even though it succeeds to some degree in achieving high network throughput by the use of SRAM to hide the long write latency of STT-MRAM. In this thesis, we propose a novel input buffer design that depends solely on STT-MRAM without the need of SRAM to maximize the benefits of low leakage power and area efficiency inherent in STT-MRAM. In addition, we introduce power-efficient buffer refreshing schemes synergized with age-based switch arbitration that gives higher priority to older flits to remove unnecessary refreshing operations. On an average, we observed throughput improvements of 16% on synthetic workloads and benchmarks.

Network-on-Chip (NoC) is a de facto inter-core communication infrastructure for future Chip Multiprocessors (CMPs). NoC should be designed to provide both low latency and high bandwidth considering limited on-chip power and area budgets. The use of a high density and low leakage memory, Spin-Torque Transfer Magnetic RAM (STT-MRAM), in NoC routers has been proposed as it increases network throughput by providing more buffer capacities with the same die footprint. However, the inevitable use of SRAM to hide the long write latencies of STT-MRAM sacrifices buffer area and also wastes significant leakage and dynamic power in migrating flits between the disparate memories. In this thesis, the first NoC router designs that use only STT-MRAM is proposed. This allows for a much larger buffer space with the least power consumptions. To overcome the multi-cycle writes, a multi-banked STT-MRAM buffer is employed, which is a logically divided virtual channel where every incoming flit is seamlessly pipelined to each bank alternately every clock cycle simple latches inside the router links. Our STT-MRAM has aggressively reduced retention time, resulting in a significant reduction in latency and power overheads of write operations. We observe flit losses in our STT-MRAM buffer, and propose cost-efficient dynamic buffer refresh schemes to minimize unnecessary refreshes with minimum hardware overheads. Simulation results show that our STT-MRAM NoC router enhances the throughput by 21.6% and achieves 61% savings in dynamic power and 18% savings in total router power, respectively compared to a conventional SRAM based NoC router of same area.

Avec la réduction continue des dimensions des transistors CMOS, le développement des mémoires statiques du type SRAM énergétiquement efficientes et de hautes densités devient de plus en plus difficile. Les dernières années ont vu l'apparition de nouvelles technologies de mémoire, qui ont attiré l'intérêt de la communauté académique, ainsi que de nombreux acteurs industriels. Parmi ces technologies, la STT-MRAM se distingue pour ses caractéristiques très avantageuses, comme sa faible consommation, ses performances et sa facilité d'intégration dans une technologie de fabrication CMOS. En plus, les MRAMs sont des technologies non-volatiles, avec une endurance élevée, nous allons utiliser cette caractéristique pour proposer de nouvelles fonctionnalités aux systèmes intégrés, notamment sur les architectures de processeur et les dispositifs reconfigurables.Une comparaison entre plusieurs amplificateurs de lecture, utilisables pour concevoir des matrices de mémoire et des cellules séquentielles a été aussi menée. Afin de démontrer la faisabilité de la conception hybride CMOS/MRAM plusieurs prototypes ont été conçus sur une technologie 28nm CMOS FDSOI et une technologie magnétique capable de produire des MTJ perpendiculaires STT de 200nm. Nous avons appliqué ces briques de base au monde du processeur notamment en proposant un processeur capable de conserver un état sain lors d'une erreur d'exécution. Les résultats obtenus confirment que le surcout de ces techniques est tout à fait compatible avec la démarche de conception d'un circuit intégré actuel. / With the downscaling of the CMOS technology, it is becoming increasingly difficult to design power-efficient and dense static random-access memories (SRAM). In the last two decades, alternative memory technologies have been actively researched both by academia and industry. Among them, STT-MRAM is one of the most promising, having near-zero static power consumption, competitive performance with respect to SRAM and easy integration with CMOS fabrication processes. Furthermore, MRAM is a non-volatile memory technology, providing for new features and capabilities when embedded in reconfigurable devices or processors. In this thesis, applications of MRAM to embedded processors and field-programmable gate-arrays (FPGAs) were investigated. A comparison of several self-referenced read circuits, with application for both memory arrays and sequential cells is provided, based on MTJ compact models provided by our project partners. To demonstrate the feasibility of the proposed circuits, we laid-out and fabricated independent, self-contained sequential cells and a hybrid, multi-context CMOS/MTJ memory array, using state-of-the-art 28nm FDSOI CMOS technology, combined with a 200nm perpendicular STT-MTJ process. Finally, we used these building blocks to implement instant on/off and backward-error recovery capabilities in an embedded processor. Results obtained by simulation allowed us to verify that these features have minimal impact on performance. An initial layout implementation allowed us to estimate the impact on silicon footprint, which could be further reduced by improvements in the MTJ integration process.

De nos jours, des efforts majeurs pour la conception de systèmes sur puces performants et efficaces énergétiquement sont en cours. Le déclin de la loi de Moore au début du XX e siècle a poussé les concepteurs à augmenter le nombre de cœurs par processeur pour continuer d’améliorer les performances. En conséquence, la surface de silicium occupée par les mémoires caches a augmentée. La finesse de gravure toujours plus petite a également fait augmenter le courant de fuite des transistors CMOS. Ainsi, la consommation énergétique des mémoires occupe une part de plus en plus importante dans la consommation globale des puces. Pour diminuer cette consommation, de nouvelles technologies de mémoires émergent depuis une dizaine d’années : les mémoires non volatiles (NVM). Ces mémoires ont la particularité d’avoir un courant de fuite très faible comparé aux technologies CMOS classiques. De fait, leur utilisation dans une architecture permettrait de diminuer la consommation globale de la hiérarchie de caches. Cependant, ces technologies souffrent de latences d’accès plus élevées que la SRAM, de coûts énergétiques d’accès plus importants et d’une durée de vie limitée. Leur intégration à des systèmes sur puces nécessite de continuer à rechercher des solutions. Cette thèse cherche à évaluer l’impact d’un changement de technologie dans la hiérarchie de caches.Plus spécifiquement, elle s’intéresse au cache de dernier niveau (LLC) et la technologie non volatile considérée est la STT-MRAM. Nos travaux adoptent un point de vue architectural dans lequel une modification de la technologie n’est pas retenue. Nous cherchons alors à intégrer les caractéristiques différentes de la STT-MRAM lors de la conception de la hiérarchie mémoire. Une première étude a permis de mettre en place un cadre d’exploration architectural pour des systèmes contenant des mémoires émergentes. Une seconde étude sur les optimisations architecturales au niveau du LLC a été menée pour identifier quelles sont les opportunités d’intégration de la STT-MRAM. Le but est d’améliorer l’efficacité énergétique tout en atténuant les pénalités d’accès dues aux fortes latences de cette technologie. / Today, intensive efforts to design energy-efficient and high-performance systems-on-chip (SoCs) are underway. Moore’s end in the early 20 th century pushed designers to increase the number of core per processor to continue to improve the performance. As a result, the silicon area occupied by cache memories has increased. The ever smaller technology node also increased the leakage current of CMOS transistors. Thus, the energy consumption of memories represents an increasingly important part in the overall consumption of chips.To reduce this energy consumption, new memory technologies have emerged overthe past decade : non-volatile memories (NVM). These memories have the particularity of having a very low leakage current compared to conventional CMOS technologies. In fact, their use in an architecture would reduce the overall consumption of the cache hierarchy. However, these technologies sufferfrom higher access latencies than SRAM, higher access energy costs and limitedlifetime. Their integration into SoCs requires a continuous research effort.This thesis work aims to evaluate the impact of a change in technology in the cache hierarchy. More specifically, we are interested in the Last-Level Cache(LLC) and we consider the STT-MRAM technology. Our work adopts an architectural point of view in which a modification of the technology is not retained. Then,we try to integrate the different characteristics of the STT-MRAM atarchitectural level when designing the memory hierarchy. A first study set upan architectural exploration framework for systems containing emerging memories. A second study on architectural optimizations at LLC was conducted toidentify opportunities for the integration of STT-MRAM. The goal is to improve energy efficiency while reducing access penalties due to the high latency ofthis technology.

La plupart des efforts de développements actuels des STT-MRAM est centrée sur des jonctions tunnels magnétiques à aimantation hors du plan. Les derniers empilements mis au point utilisent avantageusement l’anisotropie perpendiculaire induite aux interfaces magnétiques métal / oxydes, qui permet de réconcilier la forte anisotropie demandée pour assurer une rétention suffisante de la mémoire ainsi qu’une faible densité de courant de retournement STT grâce au couplage spin-orbite faible. Cependant, pour des cellules mémoire de taille inférieure à 20 nm, il est difficile d’atteindre une rétention de 10 ans à 100°C en utilisant uniquement l’anisotropie interfaciale. Pour augmenter encore plus l’anisotropie magnétique, ceci impose l’utilisation de couches magnétiques de CoFeB ultraminces (épaisseur inférieure à 1.4nm) qui présentent un coefficient d’amortissement Gilbert augmenté ainsi qu’une magnétorésistance tunnel TMR réduite. Pour des nœuds technologiques inférieurs à 20 nm, des nouveaux matériaux présentant une forte anisotropie magnétocrystalline et faible coefficient d’amortissement doivent être trouvés. De plus, l’anisotropie interfaciale est très sensible aux propriétés structurelles et chimiques aux interfaces entre les métaux magnétiques et la barrière tunnel de MgO. Avec des techniques de nanofabrication conventionnelles, ces interfaces peuvent être endommagées durant notamment l’étape de gravure, ce qui conduit à une variabilité importante cellule à cellule. Pour résoudre ce genre de problèmes pour des cellules STT-MRAM de tailles très petites, nous proposons l’utilisation d’empilements jonctions tunnel magnétiques dans lesquels l’anisotropie de la couche de stockage est contrôlée uniquement par son anisotropie de forme hors du plan. Ceci donne notamment une couche de stockage de forme cylindrique avec un aspect de forme suffisamment large (épaisseur / diamètre environ > 1). De cette façon, pour des raisons purement magnétostatiques, l’aimantation de la couche de stockage sera orientée perpendiculairement au plan de la cellule. Dans cette approche, la géométrie planaire classique des couches minces est ainsi remplacée par une géométrie tridimensionnelle. Cette approche innovante a plusieurs avantages : (i) elle génère une source fiable et robuste d’anisotropie perpendiculaire, beaucoup moins sensible aux défauts de structure et aux fluctuations thermiques; (ii) permet d’utiliser des matériaux connus et facile à croître, avec des coefficients d’amortissement faible, comme le Permalloy, en combinaison avec du CoFeB aux interfaces avec la barrière tunnel de MgO et (iii) donne une approche miniaturisable, même à des diamètres sub-10 nm, car le même matériau peut être utilisé pour des nœuds technologiques très petits. / Most of the actual STT-MRAM development effort is nowadays focused on out-of-plane magnetized MTJ taking advantage of the perpendicular magnetic anisotropy (PMA) arising at magnetic metal/oxide interface. This interfacial anisotropy allows conciliating large anisotropy required to insure a sufficient retention of the memory together with low switching current density thanks to weak spin-orbit coupling. However this PMA is too weak to insure 10 year retention up to 100°C in sub-20 nm devices. For deeply sub-20 nm nodes, new materials with large bulk PMA and low damping still have to be found. Furthermore, because this PMA is an interfacial effect, it is very sensitive to the structural and chemical properties of the magnetic metal/MgO interfaces contributing to dot to dot variability. To solve these problems in very small feature size STT-MRAM, we propose a totally novel approach: use MTJ stacks in which the storage layer anisotropy is uniquely controlled by its out-of-plane shape anisotropy i.e. by giving the storage layer a cylindrical shape with large enough aspect ratio (thickness / diameter typically > 1). In such structure, for purely magnetostatic reasons, the storage layer magnetization lies out-of-plane. With this approach, the geometry of conventional 2D thin layers is thus replaced by a 3D geometry. This innovative approach had several advantages: (i) it creates a strong and robust source of perpendicular anisotropy, much less sensitive to interfacial defects and thermal fluctuations; (ii) allows the use of well-known materials with mastered growth and low magnetic damping, such as Permalloy in combination with FeCoB at the interface of the MgO tunnel barrier and (iii) yields to an extreme scalability of the memory point, down to the sub-10 nm node, as the same materials can be used at very low nodes.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

<p>Modern computing platforms, from servers to mobile devices, demand ever-increasing amounts of memory to keep up with the growing amounts of data they process, and to bridge the widening processor-memory gap. A large and growing fraction of chip area and energy is expended in memories, which face challenges with technology scaling due to increased leakage, process variations, and unreliability. On the other hand, data intensive workloads such as machine learning and data analytics pose increasing demands on memory systems. Consequently, improving the energy-efficiency and performance of memory systems is an important challenge for computing system designers.</p> <p>Spintronic memories, which offer several desirable characteristics - near-zero leakage, high density, non-volatility and high endurance - are of great interest for designing future memory systems. However, these memories are not drop-in replacements for current memory technologies, viz. Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). They pose unique challenges such as variable access times, and require higher write latency and write energy. This dissertation explores new approaches to improving the energy efficiency of spintronic memory systems.</p> <p>The dissertation first explores the design of approximate memories, in which the need to store and access data precisely is foregone in return for improvements in energy efficiency. This is of particular interest, since many emerging workloads exhibit an inherent ability to tolerate approximations to their underlying computations and data while still producing outputs of acceptable quality. The dissertation proposes that approximate spintronic memories can be realized either by reducing the amount of data that is written to/read from them, or by reducing the energy consumed per access. To reduce memory traffic, the dissertation proposes approximate memory compression, wherein a quality-aware memory controller transparently compresses/decompresses data written to or read from memory. For broader applicability, the quality-aware memory controller can be programmed to specify memory regions that can tolerate approximations, and conforms to a specified error constraint for each such region. To reduce the per-access energy, various mechanisms are identified at the circuit and architecture levels that yield substantial energy benefits at the cost of small probabilities of read, write or retention failures. Based on these mechanisms, a quality-configurable Spin Transfer Torque Magnetic RAM (STT-MRAM) array is designed in which read/write operations can be performed at varying levels of accuracy and energy at runtime, depending on the needs of applications. To illustrate the utility of the proposed quality-configurable memory array, it is evaluated as an L2 cache in the context of a general-purpose processor, and as a scratchpad memory for a domain-specific vector processor.</p> <p>The dissertation also explores the design of caches with Domain Wall Memory (DWM), a more advanced spintronic memory technology that offers unparalleled density arising from a unique tape-like structure. However, this structure also leads to serialized access to the bits in each bit-cell, resulting in increased access latency, thereby degrading overall performance. To mitigate the performance overheads, the dissertation proposes a reconfigurable DWM-based cache architecture that modulates the active bits per tape with minimal overheads depending on the application's memory access characteristics. The proposed cache is evaluated in a general purpose processor and improvements in performance are demonstrated over both CMOS and previously proposed spintronic caches.</p> <p>In summary, the dissertation suggests directions to improve the energy efficiency of spintronic memories and re-affirms their potential for the design of future memory systems.</p>