Avec la réduction continue des dimensions des transistors CMOS, le développement des mémoires statiques du type SRAM énergétiquement efficientes et de hautes densités devient de plus en plus difficile. Les dernières années ont vu l'apparition de nouvelles technologies de mémoire, qui ont attiré l'intérêt de la communauté académique, ainsi que de nombreux acteurs industriels. Parmi ces technologies, la STT-MRAM se distingue pour ses caractéristiques très avantageuses, comme sa faible consommation, ses performances et sa facilité d'intégration dans une technologie de fabrication CMOS. En plus, les MRAMs sont des technologies non-volatiles, avec une endurance élevée, nous allons utiliser cette caractéristique pour proposer de nouvelles fonctionnalités aux systèmes intégrés, notamment sur les architectures de processeur et les dispositifs reconfigurables.Une comparaison entre plusieurs amplificateurs de lecture, utilisables pour concevoir des matrices de mémoire et des cellules séquentielles a été aussi menée. Afin de démontrer la faisabilité de la conception hybride CMOS/MRAM plusieurs prototypes ont été conçus sur une technologie 28nm CMOS FDSOI et une technologie magnétique capable de produire des MTJ perpendiculaires STT de 200nm. Nous avons appliqué ces briques de base au monde du processeur notamment en proposant un processeur capable de conserver un état sain lors d'une erreur d'exécution. Les résultats obtenus confirment que le surcout de ces techniques est tout à fait compatible avec la démarche de conception d'un circuit intégré actuel. / With the downscaling of the CMOS technology, it is becoming increasingly difficult to design power-efficient and dense static random-access memories (SRAM). In the last two decades, alternative memory technologies have been actively researched both by academia and industry. Among them, STT-MRAM is one of the most promising, having near-zero static power consumption, competitive performance with respect to SRAM and easy integration with CMOS fabrication processes. Furthermore, MRAM is a non-volatile memory technology, providing for new features and capabilities when embedded in reconfigurable devices or processors. In this thesis, applications of MRAM to embedded processors and field-programmable gate-arrays (FPGAs) were investigated. A comparison of several self-referenced read circuits, with application for both memory arrays and sequential cells is provided, based on MTJ compact models provided by our project partners. To demonstrate the feasibility of the proposed circuits, we laid-out and fabricated independent, self-contained sequential cells and a hybrid, multi-context CMOS/MTJ memory array, using state-of-the-art 28nm FDSOI CMOS technology, combined with a 200nm perpendicular STT-MTJ process. Finally, we used these building blocks to implement instant on/off and backward-error recovery capabilities in an embedded processor. Results obtained by simulation allowed us to verify that these features have minimal impact on performance. An initial layout implementation allowed us to estimate the impact on silicon footprint, which could be further reduced by improvements in the MTJ integration process.

Spin transfer torque magnetic random access memory (STT-MRAM) is a competitive, future memory technology that has gained immense interest in recent years due to its small cell size, voltage and process compatibility with CMOS and nano-second read/write speeds. It exhibits high density (3-4x of SRAM), non-volatility and process scalability and hence is widely being considered as a viable alternative for SRAM in last-level caches. As the design and fabrication process matures for the STT-MRAM, there is a need to study the various fault models that can affect this novel memory technology. This work presents a comprehensive analysis of fault models in STT-MRAM under both parametric variations as well as resistive defects (opens and shorts). Sensitivity of read, write and retention to process parameter variations such as lithographic and material variations are studied. In addition, defects (both intra-cell and inter-cell) and the corresponding fault models have been studied and data patterns which excite these faults are explored.

As Chip Multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) is a major bottleneck in CMP design. An emerging non-volatile memory - STT MRAM (Spin-Torque Transfer Magnetic RAM) which provides substantial power and area savings, near zero leakage power, and displays higher memory density compared to conventional SRAM. But STT-MRAM suffers from inherit drawbacks like multi cycle write latency and high write power consumption. So, these problem have to addressed in order to have an efficient design to incorporate STT-MRAM for NoC input buffer instead of traditional SRAM based input buffer design. Motivated by short intra-router latency, previously proposed write latency reduction technique is explored by sacrificing retention time and a hybrid design of input buffers using both SRAM and STT-MRAM to "hide" the long write latency efficiently is proposed. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer is also proposed.

Ulm, Univ., Diss., 2008.

Cette thèse s'inscrit dans la thématique des TA-MRAM, nouvelles mémoires non volatiles qui utilisent des impulsions de courant pour chauffer et ainsi permettre le renversement de l'aimantation d'une couche ferromagnétique. Un premier but de ce travail a été de comprendre les mécanismes d'écriture (chauffage) des cellules TA-MRAM. Mesures électriques et simulations thermiques sont alors comparées. De manière générale les TA-MRAM associent deux couches ferromagnétiques dont les directions relatives des aimantations sont stabilisées par des couches antiferromagnétiques. Une action développement matériaux a été menée dans la conception de jonctions tunnel magnétiques utilisant l'alliage FeMn dans la couche de stockage. Nous avons alors cherché à optimiser les couches ferromagnétiques et antiferromagnétique de la couche de stockage afin de minimiser le champ magnétique nécessaire au renversement de l'aimantation de ces couches et donc de diminuer la consommation d'énergie. Enfin ce manuscrit présente une partie gravure par faisceau d'ion (IBE) de points mémoires magnétiques qui donnent les clefs de fabrication des mémoires MRAM. / This thesis addresses a current topic of TA-MRAM, new non volatile memories using pulses to heat and thus allows the reversal of the magnetization of a ferromagnetic layer. A first goal was to learn the writing mechanism (heating) of TA-MRAM cells. Therefore, we compared electrical measurements and thermal simulations. Generally speaking, TA-MRAM combines two ferromagnetic layers where the relative direction of the magnetization is pinned by antiferromagnetic layers. Moreover, we developed new magnetic tunnel junctions using FeMn in the storage layer. We thus optimized the ferromagnetic and antiferromagnetic layers of the storage layer in order to minimize the magnetic field needed to reverse the magnetization of these layers and thus to decrease the power consumption. To finish, the etching of magnetic memory dots is explored, giving the pattern key of magnetic devices.

De nos jours, les mémoires occupent une grande superficie en silicium dans les System-on-Chip. Très largement utilisés, les mémoires Flash non volatiles présentent encore plusieurs inconvénients. Les MRAMs permettent de répondre à toutes les problématiques liées aux Flash. Cependant, elles sont sujettes à des défauts comme tout autre type de mémoire. Très peu de travaux portent sur le test de MRAM et la recherche effectuée dans ce domaine vise principalement la première génération de mémoires magnétiques. Dans ce travail, la physique derrière la modélisation MTJ est abordée. Cette compréhension est le point de départ pour développer un modèle fiable. Le MTJ est l'élément de base pour les technologies MRAM. L'injection de défauts résistif ouvert, résistif courts-circuits et capacitives ont été réalisées dans le but d'analyser les mécanismes de défaillance spécifiques de la TAS-MRAM. Un test du type march spécifique est proposé à l'aide des résultats d'analyses d'injection de défauts et de l'association de chaque mécanisme de défaillance à un modèle de défaut fonctionnel spécifique. L'évolution du TAS-MRAM est la MRAM à base MLU qui est également développée par Crocus Technology. Finalement, un modèle MLU-MTJ sera élaboré et discuté. / Memories occupy most of the silicon area in nowadays System-on-Chips. Though widely used, non-volatile Flash memories still have several drawbacks. MRAMs have the potential to mitigate almost all Flash related issues. However, they are prone to defects as any other kind of memory. Only few studies on MRAM testing can be found in the literature, and target mainly the first generation of Magnetic Memories.In this work the physics behind MTJ modeling is discussed in this work as this understanding is the starting point in order to develop a reliable model. MTJ is the basic building block of MRAMs. Moreover, Resistive-open, resistive-bridge and capacitive of defect injection are performedin order to analyze specific failure mechanisms of TAS-MRAMs. As result of defect injection analyses and the association of each failure mechanism to a specific functional fault model, a specific march test is proposed. The evolution of TAS-MRAMs is the MLU based MRAM also developed by Crocus Technology. Finally, a MLU-MTJ model will be developed and discussed.

De par la réduction continuelle des dimensions du transistor CMOS, concevoir des systèmes sur puce (SoC) à la fois très denses et énergétiquement efficients devient un réel défi. Concernant la densité, réduire la dimension du transistor CMOS est sujet à de fortes contraintes de fabrication tandis que le coût ne cesse d'augmenter. Concernant l'aspect énergétique, une augmentation importante de la puissance dissipée par unité de surface frêne l'évolution en performance. Ceci est essentiellement dû à l'augmentation du courant de fuite dans les transistors CMOS, entraînant une montée de la consommation d'énergie statique. En observant les SoCs actuels, les mémoires embarquées volatiles tels que la SRAM et la DRAM occupent de plus en plus de surface silicium. C'est la raison pour laquelle une partie significative de la puissance totale consommée provient des composants mémoires. Ces deux dernières décennies, de nouvelles mémoires non volatiles sont apparues possédant des caractéristiques pouvant aider à résoudre les problèmes des SoCs actuels. Parmi elles, la MRAM est une candidate à fort potentiel car elle permet à la fois une forte densité d'intégration et une consommation d'énergie statique quasi nulle, tout en montrant des performances comparables à la SRAM et à la DRAM. De plus, la MRAM a la capacité d'être non volatile. Ceci est particulièrement intéressant pour l'ajout de nouvelles fonctionnalités afin d'améliorer l'efficacité énergétique ainsi que la fiabilité. Ce travail de thèse a permis de mener une exploration en surface, performance et consommation énergétique de l'intégration de la MRAM au sein de la hiérarchie mémoire d'un processeur. Une première exploration fine a été réalisée au niveau mémoire cache pour des architectures multicoeurs. Une seconde étude a permis d'évaluer la possibilité d'intégrer la MRAM au niveau registre pour la conception d'un processeur non volatile. Dans le cadre d'applications des objets connectés, de nouvelles fonctionnalités ainsi que les intérêts apportés par la non volatilité ont été étudiés et évalués. / With the downscaling of the complementary metal-oxide semiconductor (CMOS) technology,designing dense and energy-efficient systems-on-chip (SoC) is becoming a realchallenge. Concerning the density, reducing the CMOS transistor size faces up to manufacturingconstraints while the cost increases exponentially. Regarding the energy, a significantincrease of the power density and dissipation obstructs further improvement inperformance. This issue is mainly due to the growth of the leakage current of the CMOStransistors, which leads to an increase of the static energy consumption. Observing currentSoCs, more and more area is occupied by embedded volatile memories, such as staticrandom access memory (SRAM) and dynamic random access memory (DRAM). As a result,a significant proportion of total power is spent into memory systems. In the past twodecades, alternative memory technologies have emerged with attractive characteristics tomitigate the aforementioned issues. Among these technologies, magnetic random accessmemory (MRAM) is a promising candidate as it combines simultaneously high densityand very low static power consumption while its performance is competitive comparedto SRAM and DRAM. Moreover, MRAM is non-volatile. This capability, if present inembedded memories, has the potential to add new features to SoCs to enhance energyefficiency and reliability. In this thesis, an area, performance and energy exploration ofembedding the MRAM technology in the memory hierarchy of a processor architectureis investigated. A first fine-grain exploration was made at cache level for multi-core architectures.A second study evaluated the possibility to design a non-volatile processorintegrating MRAM at register level. Within the context of internet of things, new featuresand the benefits brought by the non-volatility were investigated.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

This thesis explores means of mitigating the effects of silicon variation on SRAM by means of circuit techniques. This thesis also explores novel read and write techniques for MRAM that support a non-destructive read operation and power-saving write operations in the face of device and silicon variation. First, this thesis proposes the use of a cross-coupled bit line BL biasing scheme that retains an SRAM's fast access speed while reducing the read-access failures in the presence of Vt variation, without excessively increasing the SRAM cell size. It is shown, by extensive Monte-Carlo simulations using 22-nm predictive CMOS models, that the proposed scheme reduces the cell area by 6.5% compared to the conventional BL biasing schemes also analyzed. Second, this thesis proposes a 10T SRAM cell that supports lower voltage operation, achieves lower static power dissipation, and is similar in area to the 6T SRAM cell when the 3-sigma variation of Vt exceeds 40% of nominal Vt. The 10T cell achieves improved write functionality, in comparison to the 6T cell, by preemptively turning off the cell's power supply to the side of the cell that is being pulled low, while not disturbing any unselected cells. Write access time is not affected, as the positive-feedback required to quickly regenerate CMOS voltage levels remains intact. Finally, this thesis proposes a negative-resistance read scheme and write scheme for spin-torque-transfer (STT) MRAM. A negative resistance shunting an STT-MRAM cell guarantees a non-destructive read operation, and saves power during write operations compared with a conventional scheme. Measurements confirm an 7ns non-destructive read access time without the use of a typical sense amplifier and an average write power savings of 10.5% for a 16Kb STT-MRAM fabricated in 0.13um CMOS using a CoFeB/MgO/CoFeB MTJ.

As the number of processor cores on a chip increases with the advance of CMOS technology, there has been a growing need of more efficient Network-on-Chip (NoC) design since communication delay has become a major bottleneck in large-scale multicore systems. In designing efficient input buffers of NoC routers for better performance and power efficiency, Spin-Torque Transfer Magnetic RAM (STT-MRAM) is regarded as a promising solution due to its nature of high density and near-zero leakage power. Previous work that adopts STT-MRAM in designing NoC router input buffer shows a limitation in minimizing the overhead of power consumption, even though it succeeds to some degree in achieving high network throughput by the use of SRAM to hide the long write latency of STT-MRAM. In this thesis, we propose a novel input buffer design that depends solely on STT-MRAM without the need of SRAM to maximize the benefits of low leakage power and area efficiency inherent in STT-MRAM. In addition, we introduce power-efficient buffer refreshing schemes synergized with age-based switch arbitration that gives higher priority to older flits to remove unnecessary refreshing operations. On an average, we observed throughput improvements of 16% on synthetic workloads and benchmarks.