In this thesis, we study the concept of scalable video coding as implemented in the extension to the H.264 video coding standard. Specifically, for the spatial and quality scalability scenarios, we propose an optimization algorithm based on the Soft Decision Quantization (SDQ) concept, which aims at jointly optimizing all layers being encoded. The performance of the algorithm was assessed in an SVC implementation. Experimental results show, that the proposed method significantly improves the coding efficiency when compared to an unmodified SVC encoder.

BACKGROUND: Understanding the hemodynamics of the total cavopulmonary connection (TCPC) may lead to further optimization of the connection design and surgical planning, which in turn may lead to improved surgical outcome. While most experimental and numerical investigations have mainly focused on somewhat simplified geometries, the investigation of the flow field of true TCPC configurations is necessary for a true understanding. METHODS: This study details a manufacturing methodology yielding more accurate in vitro models that would provide a better understanding of the TCPC hemodynamics and adequate data for the validation of anatomical CFD simulations. This approach is illustrated on two different TCPC templates: an intra-atrial TCPC with a single superior vena cava (SVC) and a bilateral SVC with an extra-cardiac conduit. Power loss, flow visualization, digital particle image velocimetry (DPIV) flow measurements as well as computational fluid dynamics simulations are performed to characterize the anatomic flow structure. Additional parametric glass models of the TCPC were manufactured to help understand the fluid dynamics of the anatomical models and support the computational model validation effort. RESULTS/CONCLUSIONS: Both anatomic configurations revealed very different fluid dynamics underlining once again the need for at least one comprehensive experimental campaign per TCPC template for a good understanding of the flow phenomena. The absence of caval offset in the anatomical intra-atrial model resulted in important flow turbulence, which was enhanced by the large connection area and yielded high pressure drops and power losses. On the other hand, the bilateral SVC, which featured a smooth extra-cardiac conduit and wider vessels, led to power losses that were one order of magnitude lower than those of the anatomic intra-atrial model and a smooth flow field with lower levels of instability. The simplified glass models demonstrated that the diameter of the connecting vessels and of the pulmonary arteries in particular, was a parameter of prime importance. Finally, this study also reports on a combined experimental and numerical validation methodology, suggesting a cautious approach for the straightforward use of available CFD tools and pointing out the need for developing high resolution CFD techniques specifically tailored to tackle the complexities of cardiovascular flows.

In this paper, we propose two schemes for layer allocations to adjust the number of layers of SVC (Scalable Video Coding) segments according to the bandwidth variation in P2P video streaming networks. The first scheme is Periodical Layer Allocation (PLA) that can adjust the number of layers to fully satisfy the available bandwidth measured periodically. However, when the available bandwidth is changed abruptly, two major drawbacks may be occurred by PLA algorithm; first, the quality of video frames may become unsmooth so that users would feel uncomfortable about the picture quality, and second, the cost is increased due to the periodical measurement of the available bandwidth. Therefore, we propose Dynamic Layer Allocation (DLA), to dynamically change the time interval for adjusting SVC layers. When freeze-up occurred or when there was not enough buffer space to store the video segments during the interval, the interval would be reduced. When the interval for adjusting SVC layers was expired, available bandwidth can be determined by the number of video segments waiting in the buffer. Compared with PLA, DLA adjusts the SVC layers gracefully so that the quality of picture becomes smoother and users feel more comfortable while watching the film. We built a simulator written in C++ under two scenarios: the available bandwidth is changed abruptly and the one changed gradually. Simulation results show that the performance of PLA is quite similar to DLA when the available bandwidth is changed gradually. However, when the available bandwidth is changed abruptly, DLA can not only obtain the smoother video film but also decrease the freeze-up time significantly.

Design and implementation of TCR (Thyristor Controlled Reactor) for industrial SVC (Static VAr Compensator) systems require special design. Both power stage and control system design and implementation are thoroughly investigated in this thesis. Engineering aspects of TCR design are emphasized and supported with case studies. As the first case study / a novel, unified and relocatable SVC for open cast lignite mining in Turkey is designed, implemented and commissioned. The second case study is the first 12 pulse TCR design and implementation for ladle furnace compensation in the world. The SVC simulation results are verified by data acquired in the field. Real time data are also simulated in EMTDC/PSCAD program to verify the control system responses of the commissioned systems.

Power quality issues of heavy industry, especially iron and steel plants, require special solutions. High levels of harmonic currents, unbalanced operation and light flicker arising from rapid fluctuations of active and reactive power demands are common problems in these plants. Almost all of these plants in Turkey are equipped with modern Static Var Compensator (SVC) Systems. In this thesis, alternative control strategies and flicker compensation system topologies are investigated and evaluated based on real-time field data and compared with the existing SVC systems. It is found out that the currently installed SVCs are not fully capable of solving the power quality issues of EAFs. This thesis is dedicated to detailed analysis, design, control, and simulation of TCR based SVC using instantaneous power theory, Three Phase Bridge Connected STATCOM and Delta Connected STATCOM. These 3 different types of compensators are modelled based on the similar installed capacities and their contribution to voltage quality and reactive power compensation are compared.

In this thesis, we study the concept of scalable video coding as implemented in the extension to the H.264 video coding standard. Specifically, for the spatial and quality scalability scenarios, we propose an optimization algorithm based on the Soft Decision Quantization (SDQ) concept, which aims at jointly optimizing all layers being encoded. The performance of the algorithm was assessed in an SVC implementation. Experimental results show, that the proposed method significantly improves the coding efficiency when compared to an unmodified SVC encoder.

Η παρούσα διπλωματική εργασία πραγματοποιήθηκε κατά το διάστημα 11/2011-9/2012 στα πλαίσια των ερευνητικών δραστηριοτήτων του εργαστηρίου Παραγωγής, Μεταφοράς, Διανομής και Χρησιμοποίησης Ηλεκτρικής Ενέργειας του τμήματος Ηλεκτρολόγων Μηχανικών και Τεχνολογίας Υπολογιστών του Πανεπιστημίου Πατρών, υπό την επίβλεψη του καθηγητή Γαβριήλ Β. Γιαννακόπουλου. Σκοπός της εργασίας είναι η σύγκριση της δυναμικής συμπεριφοράς ενός συμβατικού σύγχρονου αντισταθμιστή και ενός εγκάρσιου στατικού αντισταθμιστή αέργου ισχύος (SVC) σε ένα εγκατεστημένο ηλεκτρικό δίκτυο, προσομοιώνοντας διαφορετικές περιπτώσεις που επηρεάζουν την διαδικασία αντιστάθμισης αέργου ισχύος και υποστήριξης τάσης σε ζυγούς του δικτύου. Στην εργασία αυτή παρουσιάζονται το μαθηματικό μοντέλο του σύγχρονου αντισταθμιστή, οι επαγωγικές παράμετροι που το χαρακτηρίζουν, τα διαφορετικά μοντέλα συστημάτων διέγερσης που χρησιμοποιούνται και ο Μετασχηματισμός Park. Όσον αφορά τον εγκάρσιο στατικό αντισταθμιστή (SVC) παρουσιάζονται οι βασικές αρχές ελέγχου των TCR και TSC που διαθέτει, η χαρακτηριστική τάσης-ρεύματος και γίνεται μια αναλυτική περιγραφή των συνιστωσών του συστήματος ελέγχου του, όπως ο ρυθμιστής τάσης, το σύστημα συγχρονισμού και η γεννήτρια παραγωγής παλμών. Τέλος, για την μοντελοποίηση και την προσομοίωση των αντισταθμιστών και του ηλεκτρικού δικτύου χρησιμοποιείται το πρόγραμμα PSCAD/EMTDC λόγω της αξιοπιστίας και της ευχρηστίας του σε μεγάλος εύρος ενεργειακών μελετών. / The current thesis was held during the period 11/2011-9/2012 within the research activities of the Generation, Transmission, Distribution and Utilization of Electric Energy Laboratory, Department of Electrical and Computer Engineering, University of Patras, under the supervision of Professor Gabriel B. Giannakopoulos. The purpose of this study is to compare the dynamic performance of a conventional synchronous condenser and a static reactive power compensator (SVC) on an installed electrical grid, simulating different cases affecting the process of reactive power compensation and voltage support at the network’s load buses. This thesis includes representation of the mathematical model of the conventional synchronous condenser and the inductive parameters that characterize it, the different excitation system models used and the Park Transformation. Regarding the static VAR compensator (SVC), this thesis also refers to the fundamentals of TCR and TSC control, the explanation of the current-voltage characteristic and the analytic description of the control system’s components, such as the voltage regulator, the synchronization system and the gate-pulse generator. Lastly, for the modeling and simulation of both compensators and the installed electrical grid, the simulation program used is PSCAD / EMTDC because of its usability and reliability on a wide range of energy projects.

Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real. / New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.

Novas arquiteturas de hardware desenvolvidas para blocos chave do padrão de codificação de vídeo ISO/IEC 14496-10 são discutidas, propostas, implementadas e validades nesta tese. Também chamado de H.264, AVC (Advanced Video Coder) ou MPEG-4 parte 10, o padrão é o estado da arte em codificação de vídeo, apresentando as mais altas taxas de compressão possíveis por um compressor de vídeo padronizado por organismos internacionais (ISO/IEC e ITU-T). O H.264 já passou por três revisões importantes: na primeira foram incluídos novos perfis, voltados para a extensão da fidelidade e aplicações profissionais, na segunda veio o suporte a escalabilidade (SVC – Scalable Video Coder). Uma terceira revisão suporta fontes de vídeo com múltiplas vistas (MVC – Multi-view Video Coder). Nesta tese são apresentadas arquiteturas para dois módulos do codificador H.264: o CABAC e o Filtro de Deblocagem (Deblocking Filter). O CABAC (Context-Adaptive Binary Arithmetic Coder) possui desafios importantes devido às dependências de dados de natureza bit-a-bit. Uma revisão das alternativas arquiteturais e uma solução específica para a codificação CABAC é apresentada nesta tese. O filtro de deblocagem também apresenta diversos desafios importantes para seu desenvolvimento e foi alvo de uma proposta arquitetural apresentada neste trabalho. Finalmente a arquitetura de uma plataforma de validação genérica para validar módulos desenvolvidos para o codificador e decodificador H.264 também é apresentada. Os módulos escolhidos estão de acordo com os demais trabalhos realizados pelo grupo de pesquisa da UFRGS, que têm por objetivo desenvolver um decodificador e um codificador completos capazes de processar vídeo digital de alta definição no formato 1080p em tempo real. / New hardware architectures developed for key blocks of the ISO/IEC 14496-10 video coding standard are discussed, proposed, implemented, and validated in this thesis. The standard is also called H.264, AVC (Advanced Video Coder) or MPEG-4 part 10, and is the state-of-the-art in video coding, presenting the highest compression ratios achievable by an internationally standardized video coder (ISO/IEC and ITU-T). The H.264 has already been revised three times: the first included new profiles for fidelity extension and professional applications. The second brought the scalability support (SVC – Scalable Video Coder). The third revision supports video sources with multiple views (MVC – Multi-view Video Coder). The present work developed high performance architectures for CABAC (Context-Adaptive Binary Arithmetic Coder), which were challenging because of the bitwise data dependencies. A through revision of the alternative architectures and a specific architectural solution for CABAC encoding are presented in this thesis. A dedicated hardware architecture for a HIGH profile Deblocking Filter is also presented, developed, validated and synthesized for two different targets: FPGA and ASIC. The validation methodology is presented and applied to three different modules of the H.264 encoder. The H.264 blocks dealt with in this thesis work complement those developed by other works in the UFRGS research group and contribute to the development of complete encoders for real-time processing of high definition digital video at 1080p.

Submitted by MARCOS JOSÉ GONÇALVES null (marcosjg@ig.com.br) on 2018-05-22T03:01:06Z No. of bitstreams: 1 Tese Marcos Jose Goncalves FINAL.pdf: 1783203 bytes, checksum: d48ee12e54924878e9c6e28de57fb570 (MD5) / Approved for entry into archive by Cristina Alexandra de Godoy null (cristina@adm.feis.unesp.br) on 2018-05-22T12:09:34Z (GMT) No. of bitstreams: 1 goncalves_mj_dr_ilha.pdf: 1783203 bytes, checksum: d48ee12e54924878e9c6e28de57fb570 (MD5) / Made available in DSpace on 2018-05-22T12:09:34Z (GMT). No. of bitstreams: 1 goncalves_mj_dr_ilha.pdf: 1783203 bytes, checksum: d48ee12e54924878e9c6e28de57fb570 (MD5) Previous issue date: 2017-11-28 / Este trabalho apresenta um estudo sobre o controle de Sistema de Energia Elétrica (SEE) com vistas à melhoria da estabilidade transitória por meio da atuação de dispositivos FACTS, neste momento considerando os compensadores em derivação (SVC) e em série (TCSC). Propõe-se a inclusão, em dispositivos pré-existentes, a incorporação de um controle adicional visando atuação em face de transitórios eletromecânicos. A influência dos dispositivos sobre a capacidade de sincronização entre os pares de máquinas, avaliada por meio do fator de efeito é inserida na atuação dinâmica/transitória do sistema. A evolução da trajetória pós-falta do sistema é considerada em relação às fronteiras da chamada Região de Sincronização Positiva (RSP) e simulações foram realizadas usando os sistemas-teste Simétrico de duas áreas e New England para Lei de Controle proposta e conclui-se que esta é efetiva na melhoria da estabilidade transitória do Sistema de Energia Elétrica e, com aprimoramentos, poderá ser incluída em procedimentos de operação em tempo real. / The power system transient stability control is approached by means of FACTS devices, and at this first step the SVC and TCSC devices are considered. A certain device acts upon each pair of machines by means of their synchronization capability which is affected by the corresponding transfer admittance as repeated by the FACTS device. This influence is taken into account by means of a parameter named Effect Factor. The boundaries of a region surrounding the stable equilibrium point named Positive Stability Region are used as reference for critical trajectories and the control action intend to reverse the tendency of the trajectory of leaving this region. In view of the shown tested cases the results are very promising since the proposed control has conduced to improvements in fault critical clearing times and so it has potential to be included in online operation procedures.