A cluster is a group of computing resources that are connected by a single computer network and are managed as a single system. Clusters potentially have three key advantages over workstations operated in isolation—fault tolerance, load balancing and support for distributed computing. Information sharing among the cluster’s resources affects all phases of cluster administration. The thesis describes a new tool for distributing files within clusters. This tool, the Scalable and Reliable File Transfer Tool (SRFTT), uses Forward Error Correction (FEC) and multiple multicast channels to achieve an efficient reliable file transfer, relative to heterogeneous clusters. SRFTT achieves scalability by avoiding feedback from the receivers. Tests show that, for large files, retransmitting recovery information on multiple multicast channels gives significant performance gains when compared to a single retransmission channel.

Research on heterojunction (HJ) metal oxide thin film transistors (TFTs) has accelerated remarkably over the last decade due to their superior performance over their conventional single-layer (SL) counterparts. Promising results in laboratory-scale demonstrations have further triggered an increased number of investigations into fabrication and processing techniques for the large-scale integration of HJ metal oxide TFTs. Nevertheless, a lack of consensus regarding the most appropriate scalable manufacturing technique, which combines low-cost and high-throughput fabrication, holds back new opportunities for HJ metal oxide TFTs in emerging applications. In this thesis, novel approaches and strategies are introduced to facilitate the large-scale integration of HJ metal oxide TFTs. The first study of this dissertation introduces the solution-processed In2O3/ZnO heterojunction TFTs with a high-κ bilayer dielectric consisting of Al2O3/ZrO2. Processing was carried out on rigid glass as well as flexible PEN substrates via rapid flash lamp annealing (FLA) as an alternative scalable and high-throughput processing route to conventional thermal annealing. In the second study of the dissertation, a novel 3D/2D/3D mixed-dimensional channel concept was developed with the combination of scalable spray coating and FLA techniques. The insertion of sprayed MoS2 nanoflakes between flashed SnO2/ZnO HJ results in outstanding device performance with a high mobility value of 62 cm2/Vs compared to single layers as well as heterojunction metal oxide TFTs, showing maximum mobility of 4.48 cm2/Vs. In the third study, the fabrication of In2O3/ZnO heterojunction metal oxide TFTs with solution-processed conductive Ti3C2Tx MXene contacts using a processing route that fully relies on a scalable spray coating process is demonstrated as an alternative to low-throughput vacuum-based electrodes. Notably, the proposed approach was successfully upscaled to a 4-inch glass substrate, underlining the significant potential garnered by MXene electrodes for industrial-scale electronics. The last study of the dissertation exploits the advantages of the adhesion-lithography (a-Lith) technique, which enables the development of coplanar self-aligned gate (SAG) In2O3/ZnO heterojunction TFTs and their facile integration into large-area electronics. Using the a-Lith technique, coplanar SAG architectures were fabricated where the gate and dielectric (Al and Al2O3, respectively) are located side by side with the source/drain electrodes (Au), separated from each other by nanogaps.

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Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design. To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU. To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing. To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals. To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control. It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming. To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um². With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management. The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller. / Ph. D.

In this thesis we present a parallel implementation of an engineering code which simulates the deformations caused when forces are applied to a piezoelectric-controlled smart structure. The parallel simulation, whose domain decomposition relies on the finite element representation of the structure, is created with an emphasis on scalability of both memory requirements and run time. We take into consideration sequential performance enhancements, the structure of a banded symmetric positive definite linear system, and the overhead required to completely distribute the problem across the processors. The resulting code is scalable, with the exception of a banded Cholesky factorization, which does not fully utilize the parallel environment. / Master of Science

This project documents my efforts to publish STS- and gender theory-informed articles in engineering education journals. It analyzes the processes of writing and revising three articles submitted to three different journals, aiming to shed light on the field of engineering education, gender research therein, and contribute to feminist science studies literature on the challenges and opportunities of interdisciplinary work across women's studies and STEM fields. Building upon Wenger's concept of brokering, I analyze how I brought previously underexplored STS and feminist theory literature into engineering education journals. In producing this dissertation, I aim to illuminate some of the efforts and challenges of bringing STS and Women's Studies (WS) topics into engineering education journals – thus producing an account of brokering practices and an example of scalable scholarship. The first chapter introduces engineering education research (EER) as a field of inquiry, situates my project with respect to current feminist science studies, summarizes the framework of brokering that informs my analyses, and describes my methodology. The second chapter describes my initial attempts at brokering by identifying and bridging differences and the preliminary brokering practices that emerged through writing and revising the first of my three articles. It discusses an article published in Journal of Engineering Education that analyzes the uses of feminist theory in EER and argues that further engagement with a broader range of feminist theories could benefit EER. The third chapter describes how some of these practices were reinforced, but also supplemented, while writing and revising the second article. It discusses an article published in International Journal of Engineering Education that analyzes problematizations of underrepresentation in EER and argues that further reflection upon and formal discussion of how underrepresentation is framed could benefit EER. The forth chapter describes how the established brokering practices guided writing the third article, making the process easier as I had become more comfortable with the requirements and challenges of brokering. It discusses an article submitted to European Journal of Engineering Education that analyzes feminist research methodologies in the context of EER, using data from interviews with feminist engineering educators. The fifth chapter concludes by summarizing the brokering practices and discussing their respective challenges, discussing the implications of this project for STS and WS, and, finally, by discussing other implications for peer review engineering education. The Appendix contains aims, scope, author guidelines, and review criteria for the three journals. Chapters 2, 3, and 4 each begin with a narrative recounting of the practices of brokering that went into producing and revising each article. The narratives describe processes of writing and preparing to submit the articles, reviews received, and subsequent revision processes. The published or submitted articles appear after the brokering narrative. / Ph. D.