A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum. In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,…,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time. To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech. Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one. / Ph. D.

The computational power and algorithms needed to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal transmitted will follow all FCC rules. The work presented in this thesis provides a methodology to guarantee that all signals will be legal and valid. The first part to achieving this is a practical and easy to use software testing program based on the tabu search algorithm that tests the software off-line. The primary purpose of the software testing program is to find most of the errors, specially structural errors, while the radio is not in use so that it does not affect the performance of the system. The software testing program does not provide a complete assurance that no errors exist, so to supplement this deficit, a built-in self-test (BIST) is employed. The BIST is designed with two parts, one that is embedded into the cognitive engine and one that is placed into the radio's API. These two systems ensure that all signals transmitted by the cognitive radio will follow FCC rules while consuming a minimal amount of computational power. The software testing approach based on the tabu search is shown to be a viable method to test software with improved results over previous methods. Also, the software BIST demonstrated its ability to find errors in the signal production and is dem to only require an insignificant amount of computational power. Overall, the methods presented in this paper provide a complete and practical approach to assure the FCC of the legality of all signals in order to obtain a license for the product. / Master of Science

On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip (SoC). This work deals with cost-effective BIST methods and Test Pattern Generation (TPG) schemes in BIST for fault detection and diagnosis of analog circuits. Fault-based testing is used in analog domain due to the applicable test methods/ techniques being general and cost-effective. We propose a novel test method causing the Device Under Test (DUT) to saturate or get out of saturation to detect a fault with simple detection hardware. The proposed test method is best suited for use of existing building blocks in Systems-on-Chip (SoC) for implementation of an on-chip test signal generator and test response analyzer. Test generation for a fault in analog circuit is a compute intensive task. A good test generator produces a highly compact test set with less computational effort without trading the fault coverage. In this context, three new test generation methods viz., MultiDetect, ExpoTan, and MultiDiag for testing analog circuits are presented in this thesis. Testing of analog blocks based on circuit transfer function makes the proposed ATPG methods as general-purpose methods for all kinds of LTI circuits. The principle of MultiDetect method, (i.e., selecting a test signal for which the output amplitude difference between good and faulty circuits is minimum when compared to other test signals in an initial test set), helps in the generation of high quality compacted test set with less fault simulations. The experimental results show that the testing of LTI circuits using MultiDetect technique for the benchmark circuits achieves the required fault coverage with much shorter testing time. The generated test set with MultiDetect method can effectively detect both soft and hard faults and does not require any precision analog signal sources or signal measurement circuits when implemented as Built In Self Test (BIST). Test generation for a list of faults and test set compaction are two different phases in an ATPG process. To build an efficient ATPG, these two phases need to be combined with a technique such that the generated test set is highly compact and efficient with less fault simulations. In this context, a novel test set selection technique known as ExpoTan for testing Linear Time Invariant (LTI) circuits is also presented in this thesis. The test generation problem is formulated with tan-1( ) and exponential functions for identification of a test signal with maximum fault coverage. Identification of a sinusoid that detects more faults results in an optimized test signal set. Fault diagnosis and fault location in analog circuits are of fundamental importance for design validation and prototype characterization in order to improve yield through design modification. In this context, we propose a procedure viz., MultiDiag for generation of a test set for analog fault diagnosis. The analog test generation methods, viz., Max, Rand, and MultiDetect etc., which are based on sensitivity analysis, may fail at times to identify a test signal for locating a fault; because the search for a test signal using these test generation methods is restricted to the limited test signals set. But, the MultiDiag method definitely identifies a test signal, if one exists, for locating a fault.

L’évolution tendant à réduire la taille et augmenter la complexité des circuits électroniques modernes, est en train de ralentir du fait des limitations technologiques, qui génèrent beaucoup de d’imperfections et de defaults durant la fabrication ou la durée de vie de la puce. Les FPGAs sont utilisés dans les systèmes numériques complexes, essentiellement parce qu’ils sont reconfigurables et rapide à commercialiser. Pour garder une grande fiabilité de tels systèmes, les FPGAs doivent être testés minutieusement pour les defaults. L’optimisation de l’architecture des FPGAs pour l’économie de surface et une meilleure routabilité est un processus continue qui impacte directement la testabilité globale et de ce fait, la fiabilité. Cette thèse présente une stratégie complète pour le test et le diagnostique des defaults de fabrication des “mesh-based FPGA” contenant une nouvelle topologie d’interconnections à plusieurs niveaux, ce qui promet d’apporter une meilleure routabilité. Efficacité des schémas proposes est analysée en termes de temps de test, couverture de faute et résolution de diagnostique. / The evolution trend of shrinking feature size and increasing complexity in modern electronics is being slowed down due to physical limits that generate numerous imperfections and defects during fabrication steps or projected life time of the chip. Field Programmable Gate Arrays (FPGAs) are used in complex digital systems mainly due to their reconfigurability and shorter time-to-market. To maintain a high reliability of such systems, FPGAs should be tested thoroughly for defects. FPGA architecture optimization for area saving and better signal routability is an ongoing process which directly impacts the overall FPGA testability, hence the reliability. This thesis presents a complete strategy for test and diagnosis of manufacturing defects in mesh-based FPGAs containing a novel multilevel interconnects topology which promises to provide better area and routability. Efficiency of the proposed test schemes is analyzed in terms of test cost, respective fault coverage and diagnostic resolution.

With the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs. / text

Cette thèse vise l’étude de techniques de type BIST pour un front-end RF, considérant des nouveaux types des capteurs intégrés très simples pour l’extraction de signaux. Ces signaux et les stimuli de test associés seront par la suite traités par des algorithmes de l’apprentissage automatique qui devront permettre une prédiction des performances des différents blocs du système. Une évaluation des capteur proposés en tant que métriques de test paramétrique et couverture des fautes catastrophique sera nécessaire pour pouvoir aboutir à des techniques de test à bas coût pour le test de production, permettant une réduction importante du coût de revient des produits. / This thesis aims to study techniques such BIST for RF front-end, whereas new types of simple integrated sensors for signal extraction. These signals and stimuli associated test will then be processed by machine learning algorithms that will allow prediction of the performance of different blocks of the system. An evaluation of the proposed sensor as parametric test metrics and coverage of catastrophic faults will be needed to reach test techniques for low-cost production test, allowing a significant reduction in the cost of products

Work discusses about the test station in NXP Semiconductors Company in Rožnov pod Radhoštěm. It describes first the test station itself and its possibilities in software libraries testing. Second it describes automatic selftest of this station and sub-steps of this selftest. This work is also used as a documentation for company needs. KEYWORDS

Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear dependencies present in the LFSM generated test-bit sequences adversely affect the resultant fault coverage in two-dimensional scan designs. In this work, we present methods that improve the resultant fault coverage in two-dimensional scan designs through the minimization of linear dependencies. Currently, metric of channel separation and matrix-based metric are used in order to estimate linear dependencies in a CUT. When the underlying sub-circuit (cone) structure of a CUT is available, the matrix-based metric can be used more effectively. Fisrt, we present two methods that use matrix-based metric and minimize the overall linear dependencies in a CUT through explicitly minimizing linear dependencies in the highest number of underlying cones of the CUT. The first method minimizes linear dependencies in a CUT through the selection of an appropriate LFSM structure. On the other hand, the second method synthesizes a phase shifter for a specified LFSM structure such that the overall linear dependencies in a CUT are minimized. However, the underlying structure of a CUT is not always available and in such cases the metric of channel separation can be used more effectively. The metric of channel separation is an empirical measure of linear dependencies and an ad-hoc large channel separation is imposed between the successive scan chains of a two-dimensional scan design in order to minimize the linear dependencies. Present techniques use LFSMs with additional phase shifters (LFSM/PS) as PRPGs in order to obtain desired levels of channel separation. We demonstrate that Generalized LFSRs (GLFSRs) are a better choice as PRPGs compared to LFSM/PS and obtain desired levels of channel separations at a lower hardware cost than the LFSM/PS. Experimental results corroborate the effectiveness of the proposed methods through increased levels of the resultant fault coverage in two-dimensional scan designs.

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With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate external test equipment, enables the application of a large number of random tests, and allows for at-speed testing. The main problem with LBIST is suboptimal fault coverage achievable with random vectors. LFSR reseeding is used to increase the coverage. However, to achieve satisfactory coverage, one often needs a large number of seeds. Computing a small number of seeds for LBIST reseeding still remains a tremendous challenge, since the vectors needed to detect all faults may be spread across the huge LFSR vector space. In this work, we propose new methods to enable the computation of a small number of LFSR seeds to cover all stuck-at faults as a first-order satisfiability problem involving extended theories. We present a technique based on SMT (Satisfiability Modulo Theories) with the theory of bit-vectors to combine the tasks of test-generation and seed computation. We describe a seed reduction flow which is based on the `chaining' of faults instead of pre-computed vectors. We experimentally demonstrate that our method can produce very small sets of seeds for complete stuck-at fault coverage. Additionally, we present methods for inserting test-points to enhance the testability of a circuit in such a way as to allow even further reduction in the number of seeds. / Master of Science