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We report on the observation of lasing in cuprous iodide (CuI) microwires. A vapor-phase transport growth procedure was used to synthesize CuI microwires with low defect concentration. The crystal structure of single microwires was determined to be of zincblende-type. The high optical quality of single microwires is indicated by the observed series of excitonic emission lines as well as by the formation of gain under optical excitation. Lasing of triangular whispering-gallery modes in single microwires is demonstrated for fs- and ns-excitation from cryogenic temperatures up to 200 K. Timeresolved micro-photoluminescence studies reveal the dynamics of the laser process on the time scale of several picoseconds.

Al–O monolayers embedded in ultrathin SiO₂ were shown previously to contain Al-induced acceptor states, which capture electrons from adjacent silicon wafers and generate a negative fixed charge that enables efficient Si-surface passivation. Here, we show that this surface passivation is just in part attributed to field-effect passivation, since the electrically active interface trap density Dit itself at the Si/SiO₂ interface is reduced by the presence of the acceptor states. For sufficiently thin tunnel-SiO₂ films between the Si-surface and the Al–O monolayers, Dit is reduced by more than one order of magnitude. This is attributed to an interface defect deactivation mechanism that involves the discharge of the singly-occupied dangling bonds (Pb0 defects) into the acceptor states, so that Shockley-Read-Hall-recombination is drastically reduced. We demonstrate that the combined electronic and field-effect passivation allows for minority carrier lifetimes in excess of 1 ms on n-type Si and that additional H₂-passivation is not able to improve that lifetime significantly.

<div>Power semiconductor devices play an important role in many areas, including household</div><div>appliances, electric vehicles, high speed trains, electric power stations, and renewable energy</div><div>conversion. In the modern era, silicon based devices have dominated the semiconductor</div><div>market, including power electronics, because of their low cost and high performance. The</div><div>applications of devices rated 600 V - 6.5 kV are still dominated by silicon devices, but they</div><div>are nearly reaching fundamental material limits. New wide band gap materials such as silicon</div><div>carbide (SiC) offer significant performance improvements due to superior material properties</div><div>for such applications in and beyond this voltage range. 4H-SiC is a strong candidate</div><div>among other wide band gap materials because of its high critical electric field, high thermal</div><div>conductivity, compatibility with silicon processing techniques, and the availability of high</div><div>quality conductive substrates.</div><div>Vertical DMOSFETs and insulated gate bipolar transistors (IGBT) are key devices for</div><div>high voltage applications. High blocking voltages require thick drift regions with very light</div><div>doping, leading to specific on-resistance (R_ON,SP ) that increases with the square of blocking</div><div>voltage (V_BR). In theory, superjunction drift regions could provide a solution because of a</div><div>linear dependence of R_ON,SP on V_BR when charge balance between the pillars is achieved</div><div>through extremely tight process control. In this thesis, we have concluded that superjunction</div><div>devices inevitably have at least some level of charge imbalance which leads to a quadratic</div><div>relationship between V_BR and R_ON,SP . We then proposed an optimization methodology to</div><div>achieve improved performance in the presence of this inevitable imbalance.</div><div>On the other hand, an IGBT combines the benefits of a conductivity modulated drift</div><div>region for significantly reduced specific on-resistance with the voltage controlled input of a</div><div>MOSFET. Silicon carbide n-channel IGBTs would have lower conduction losses than equivalent</div><div>DMOSFETs beyond 6.5 kV, but traditionally have not been feasible below 15 kV. This</div><div>is due to the fact that the n+ substrate must be removed to access the p+ collector of the</div><div>IGBT, and devices below 15 kV have drift layers too thin to be mechanically self-supporting.</div><div>In this thesis, we have demonstrated the world’s first functional 10 kV class n-IGBT with</div><div>a waffle substrate through simulation, process development, fabrication and characterization.</div><div><div>The waffle substrate would provide the required mechanical support for this class of devices.</div><div>The fabricated IGBT has exhibited a differential R_ON,SP of 160 mohm</div><div>.cm², less than half of</div><div>what would be expected without conductivity modulation. An extensive fabrication process</div><div>development for integrating a waffle substrate into an active IGBT structure is described</div><div>in this thesis. This process enables an entirely new class of moderate voltage SiC IGBTs,</div><div>opening up new applications for SiC power devices.</div></div>

Here, silicon oxide was formed in a U-shaped trench of a power metal-oxide semiconductor field-effect transistor device by various processes. One SiO₂ formation process was performed in multiple steps to create a low-defect Si-SiO₂ interface, where first a thin initial oxide was grown by thermal oxidation followed by the deposition of a much thicker oxide layer by chemical vapor deposition (CVD). In a second novel approach, silicon nitride CVD was combined with radical oxidation to form silicon oxide in a stepwise sequence. The resulting stack of silicon oxide films was then annealed at temperatures between 1000 and 1100 °C. All processes were executed in an industrial environment using 200 mm-diameter (100)-oriented silicon wafers. The goal was to optimize the trade-off between wafer uniformity and conformality of the trenches. The thickness of the resulting silicon oxide films was determined by ellipsometry of the wafer surface and by scanning electron microscopy of the trench cross sections. The insulation properties such as gate leakage and electrical breakdown were characterized by current–voltage profiling. The electrical breakdown was found to be highest for films treated with rapid thermal processing. The films fabricated via the introduced sequential process exhibited a breakdown behavior comparable to films deposited by the common low-pressure CVD technique, while the leakage current at electric fields higher than 5 MV/cm was significantly lower.