Thesis (B.S.)--Rochester Institute of Technology, 1985. / Typescript. Includes bibliographical references (leaves 31-32).

Over the last five years, a dramatic expansion of renewable energy from Photovoltaic (PV) solar cells has been witnessed. This expansion is due in part to wafer based silicon solar cells. Crystalline silicon solar cells currently dominate the PV market because of their low cost per watt of electricity production. In order for silicon solar cells to continue to govern the market, efficiency improvements and cost reductions must be made. This work focuses on both cost reduction and efficiency improvements, for wafer based silicon solar cells. The main aim of the work was to produce a thin monocrystalline wafer based silicon solar cell. A large proportion of the cost of conventional monocrystalline solar cells is related to the use of high purity silicon substrates. By producing a cell that uses less silicon, significant cost savings can be made. Conventional wafering techniques used in industry are reaching their limit for thin wafer production. The method adopted in this work uses a simple silicon exfoliation technique capable of producing ultrathin silicon foils. A fully operational solar cell was fabricated from a 40mum exfoliated silicon foil. The thin wafer based silicon solar cell was more than four times thinner than a commercially produced equivalent. The work investigated a variety of principles related to the exfoliation and the suitability of the technique for thin photovoltaic devices. By using a thin exfoliated substrate, conventional anti-reflective (AR) suppressing processes could prove problematic. Experiments were conducted into finding an alternative technique to match the performance of the conventional AR process. The formation of porous silicon (PSi) on the surface of a silicon substrate was found not only to match the commercial process, but to exceed it. With a porous silicon layer, reflectivity was suppressed to just 6.68%. The technique could be applied to both thin silicon solar cells and conventional thicker wafer based cells. The reflectivity suppressive layer could be fabricated in a single simple processing step. Investigation was also focused upon the top contact for silicon solar cells. As the top of the cell is responsible for current collection and light absorption, large electrical contacts shade the cell resulting in a decrease in efficiency. Silver nanowires (AgNWs) were successfully analysed and deposited onto standard silicon solar cell top contacts as an enhancement coating. Such a coating was found to improve the collection ability of the top contact without causing a significant increase in shading loss. The use of an optimised AgNW coating can increase cell efficiency by as much as 37%.

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Semiconductor manufacturing is characterized by a dynamic, varying environment and the technology to produce integrated circuits is always shifting in response to the demand for faster and new products, and the time between the development of a new profitable method of manufacturing and its transfer to tangible production is very short. The semiconductor industry has adopted the use of advanced process control (APC), namely a set of automated methodologies to reach desired process goals in operating individual process steps. That is because the ultimate motivation for APC is improved device yield and a typical semiconductor manufacturing process can have several hundred unit processes, any of which could be a yield limiter if a given unit procedure is out of control. APC uses information about the materials to be processed, metrology data, and the desired output results to choose which model and control plan to employ. The current focus of APC for semiconductor manufacturers is run-to-run control. Many metrology applications have become key enablers for the conventionally labeled “value-added” processing steps in lithography and etch and are now integral parts of these processes. The economic advantage of effective metrology applications increases with the difficulty of the manufacturing process. Frequent measurement facilitates products reaching its target but it increases the cost and cycle time. If lots of measurements are skipped, the product quality does not be guaranteed due to process error from uncompensated drift and step disturbance. Thus, it is necessary to optimize the sampling plan in order to quickly identify the sources of prediction errors and decrease the metrology cost and cycle time. The goal of this research intend to understand the relationship between metrology and advanced process control (APC) in semiconductor manufacturing and develop an enhanced sampling strategy in order to maximize the value of metrology and control for critical wafer features. / text

Microdefects in wafers sliced from selected positions along Czochralski (CZ)-grown, silicon single crystal ingots were investigated by means of transmission electron microscopy (TEM). Specimens taken from the central regions of these wafers, previously subjected to specific thermal treatments, were prepared either by ultrasonic cutting and jet thinning or by an anisotropic thinning method. Ultrasonic cutting was found to generate microdefects in the thin surface regions of the TEM specimen discs. The density of ultrasonically generated defects (USD's) was found to vary directly with the ultrasonic energy input from the cutter. Ultrasonic waves transmitted through abrasive slurry into the discs, causing lattice vibrations, are believed to be responsible for the microdefect generation. Anisotropic thinning for the preparation of TEM specimens was carried out in an agitated bath of KOH-Isopropyl Alcohol (IPA)-H₂O at 80°C and 60°C. A great number of high-surface-quality, self-supporting thin films can be produced with large (about 30 mils square) electron-transparent areas. Edges of the thin films are in <110> directions and can be used as quick reference for defect orientation during electron microscopy. Specimens from heat-treated wafers disclosed the presence of precipitates measuring some 100-1500 nm on one side, surrounded by prismatic dislocations punched out in <110> directions in the crystal. The precipitates appear to be thin platelets (less than 40 Å in thickness), lying on {100} planes and are viewed either as flat squares or rectangles, or as edge-on rods inclined 45° to the <110> directions. The edges of the platelets are in <110> directions. Prismatic punched-out dislocation loops are formed in rows, the axes of which are in <110> directions. A row of loops seen edge-on is similar in size if its axis is in the surface <110> directions. When loop axes are in the oblique <110> directions from the surface, they appear as closed rhombus loops with line senses in <112> directions. Their size increases with distance from the precipitate. The observed dislocation loops were found to be of interstitial type with a Burger's vector of a/2 <110>. The total defect density (precipitates and dislocation loops) of a specimen depend strongly on the thermal history of the wafer and on the wafer position in the ingot.

by Dong, Mei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 83-90). / Abstracts in English and Chinese. / INTRODUCTION --- p.1 / Chapter 1.1 --- Bump Height Inspection --- p.1 / Chapter 1.2 --- Our Height Inspection System --- p.2 / Chapter 1.3 --- Thesis Outline --- p.3 / BACKGROUND --- p.5 / Chapter 2.1 --- Wafer Bumps --- p.5 / Chapter 2.2 --- Common Defects of Wafer Bumps --- p.7 / Chapter 2.3 --- Traditional Methods for Bump Inspection --- p.11 / BIPLANAR DISPARITY METHOD --- p.22 / Chapter 3.1 --- Problem Nature --- p.22 / Chapter 3.2 --- System Overview --- p.25 / Chapter 3.3 --- Biplanar Disparity Matrix D --- p.30 / Chapter 3.4 --- Planar Homography --- p.36 / Chapter 3.4.1 --- Planar Homography --- p.36 / Chapter 3.4.2 --- Homography Estimation --- p.39 / Chapter 3.5 --- Harris Corner Detector --- p.45 / Chapter 3.6 --- Experiments --- p.47 / Chapter 3.6.1 --- Synthetic Experiments --- p.47 / Chapter 3.6.2 --- Real image experiment --- p.52 / Chapter 3.7 --- Conclusion and problems --- p.61 / PARAPLANAR DISPARITY METHOD --- p.62 / Chapter 4.1 --- The Parallel Constraint --- p.63 / Chapter 4.2 --- Homography estimation --- p.66 / Chapter 4.3. --- Experiment: --- p.69 / Chapter 4.3.1 --- Synthetic Experiment: --- p.69 / Chapter 4.3.2 --- Real Image Experiment: --- p.74 / CONCLUSION AND FUTURE WORK --- p.80 / Chapter 5.1 --- Summary of the contributions --- p.80 / Chapter 5.2 --- Future Work --- p.81 / Publication related to this work: --- p.83 / BIBLIOGRAPHY --- p.83

This thesis addresses the use of a vibrating Kelvin probe to monitor the change in the front surface potential of a silicon wafer while the rear surface is illuminated with monochromatic, visible light. Two tests were run to verify the change in surface potential. One test increased the intensity of the light and the other increased the wavelength while recording the front surface potential. The change in the surface potential for a range of intensities of incident light was recorded and analyzed. The results show that the change in surface potential increased with increasing intensity. For each wafer, the smallest change in surface potential occurred at the lowest intensity, 3.77 mW. In the same respect, the largest change in surface potential occurred at the highest intensity, 17.8 mW. For all wafers, the change in surface potential ranged from approximately 8 mV at 3.77 mW to approximately 80 mV at 17.8 mW. The change in the surface potential for a range of wavelengths of incident light was also recorded and analyzed. The results showed that the change in surface potential formed a skewed bell curve with increasing wavelength of incident light. For each wafer, the largest change in surface potential occurred at mid-range wavelengths, between 600 nm and 700 nm. The smallest change in surface potential occurred at 450 nm, the shortest wavelength, and 800 nm, the longest wavelength. For all wafers, the change in surface potential ranged from approximately 8 mV at 800 nm to approximately 165 mV at 700 nm. A model based on excess electron diffusion within the silicon wafer was used to predict material properties. After curve fitting the model with experimental results, an excess electron lifetime of ôN = 17 µs and surface recombination rates of sFRONT = sREAR = 18,000cm/s were predicted. These values suggest poor silicon wafer quality relative to commercial silicon devices. Regardless of the quality, the results show that the front surface potential of a silicon wafer is affected by incident light on the rear surface. The quantitative effect of the light is dependent on the properties of the light and the material properties of the silicon wafer.

Thesis (M.S.)--Texas State University-San Marcos, 2008. / Vita. Includes bibliographical references (leaves 43-46). Also available on microfilm.

Thesis (Ph. D.)--School of Electrical and Computer Engineering, Georgia Institute of Technology, 2004. Directed by Gary S. May. / Includes bibliographical references.