Thesis (Ph. D.)--University of Wisconsin--Madison, 1967. / Typescript. Vita. Description based on print version record. Includes bibliographical references (leaves 130-133).

Thesis (Ph. D.)--Psychology, Georgia Institute of Technology, 2006. / Daniel Spieler, Committee Member ; Dennis Folds, Committee Member ; Arthur Fisk, Committee Chair ; Wendy Rogers, Committee Member ; Eric Schumacher, Committee Member.

Thesis (Ph.D.)(Computer Science)--University of Pretoria, 2007. / Includes summary. Includes bibliographical references. Available on the Internet via the World Wide Web.

[by] A.K. Susskind, D.R. Haring [and] C.L. Liu. / Includes bibliographies. / "AD 657370."

Thesis (MSc (Computer Science))--University of Stellenbosch, 2006. / The minimization of a Finite Automaton (FA) deals with the construction of an equivalent FA with the least number of states. Traditional FAs and the minimization thereof is a well defined and researched topic within academic literature. Recently a generalized form of the FA, namely the generalized FA(*-FA), has been derived from these traditional FAs. This thesis investigates the minimization and reduction of one case of ...

This research investigates three solutions to overcoming portability and scalability concerns in the Evolutionary Hardware (EHW) field. Firstly, the study explores if the V-FPGA—a new, portable Virtual-Reconfigurable-Circuit architecture—is a practical and viable evolution platform. Secondly, the research looks into two possible ways of making EHW systems more scalable: by optimising the system’s genetic algorithm; and by decomposing the solution circuit into smaller, evolvable sub-circuits or modules. GA optimisation is done is by: omitting a canonical GA’s crossover operator (i.e. by using an algorithm); applying evolution constraints; and optimising the fitness function. The circuit decomposition is done in order to demonstrate modular evolution. Three two-bit multiplier circuits and two sub-circuits of a simple, but real-world control circuit are evolved. The results show that the evolved multiplier circuits, when compared to a conventional multiplier, are either equal or more efficient. All the evolved circuits improve two of the four critical paths, and all are unique. Thus, it is experimentally shown that the V-FPGA is a viable hardware-platform on which hardware evolution can be implemented; and how hardware evolution is able to synthesise novel, optimised versions of conventional circuits. By comparing the and canonical GAs, the results verify that optimised GAs can find solutions quicker, and with fewer attempts. Part of the optimisation also includes a comprehensive critical-path analysis, where the findings show that the identification of dependent critical paths is vital in enhancing a GA’s efficiency. Finally, by demonstrating the modular evolution of a finite-state machine’s control circuit, it is found that although the control circuit as a whole makes use of more than double the available hardware resources on the V-FPGA and is therefore not evolvable, the evolution of each state’s sub-circuit is possible. Thus, modular evolution is shown to be a successful tool when dealing with scalability.

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This report will demonstrate the design techniques to translate a given scanning algorithm into a hardwired pre-processor. The language to be "pre-processed" is TRAC (Text Reckoning and Compiling) devised by Mooers and Deutsch. The major drawback in the current implementation of TRAC is speed. The software overhead required for string manipulations and execution of the input scanning algorithm is the major degrading factor. A TRAC machine consisting of a hardwired pre-processor to scan the input and produce formatted data for a stack oriented evaluator is proposed. The control machine for the input scanning algorithm for the pre-processor is designed using various sequential machine design techniques. The one-hot code and the minimum state variable design represent the two extremes which are presented.