The aim of this pro ject was to evaluate the use of SIMD array architectures in radar signal processing. This has been done by implementing one of the most demanding parts of the radar signal processing chain for airborne radar on the CSX600 architecture devel- oped by Clearspeed Technologies. The CSX600 architecture is a SIMD processor with 96 processing elements which can be arranged either as a linera array or as a ring. The QR- decomposition, which was the part chosen for implementation, is the most performance demanding part of the STAP stage. In order to create a relevant test case the well known RT STAP benchmark from Mitre Corporation has been used. Two different algorithms for performing QR-decompositions have been implemented and verified. In both cases it has been concluded that either longer (> ≈256) or shorter (< ≈32) processor array lengths would, in general, yield a higher utilization ratio. The FLOP count and utiliza- tion has been measured for both algorithms, and it has been concluded that at least eight CSX600 processors are needed to meet the real-time demand of the benchmark.

The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite imaging and pattern recognition. In the case of military operations, real-time image pro-cessing is extensively used in target acquisition and tracking, automatic target recognition and identi cation, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor implementation can be used in order to reduce processing time. Previous work explored several realizations of 2D denominator separable digital filters with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared. From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 by 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the denormalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources.

The objective of this thesis is to develop a low-cost infrared absorption spectroscope based on linear variable filter (LVF) technology for the automated detection of gases and vapors, and the semi-automated detection of liquids. This instrument represents an alternative to electronic-nose instruments based on cross-selective gas sensor arrays. Instead, the proposed instrument uses the idea of computational “pseudo-sensors”, whereby spectral lines in an analytical instrument are clustered into groups and used as independent variables. We characterize the system on a number of performance metrics, uncovering its detection limits and resolving power. We present calibration methods to estimate the concentration of analytes in a matrix of absorbing species, as well as signal processing techniques for spectral classification. Specifically, we validate the instrument on a mixture calibration problem with simple and complex chemicals, and compare the efficiency of different calibration methods to estimate the concentration of one analyte in the matrix. Moreover, we demonstrate the use of the instrument on two real-world applications in the foodstuffs domain: oil adulteration and trans fatty acid (TFA) detection. The instrument, combined with signal processing techniques, is able to fully discriminate oils, as well as classify margarine and spreads onto high-TFA and low-TFA groups. Despite operating at a low spectral resolution, our results show that the LVF based spectroscope is a promising alternative to traditional analytical techniques for selected niche applications.

No description available.

Power measurement is important for various purposes such as revenue metering, power quality improvement, and direct load control. Various algorithms for power measurement have been proposed in the time domain, which implies a simple instrumentation, but more useful power formulations have been derived in the frequency-domain approach which would require appropriate sampling and measurement techniques to avoid long delay in processing voltage and current signals. The aim of this thesis to implement a measurement instrument that can measure the power components digitally and efficiently under sinusoidal and non-sinusoidal situations. We will use a high performance digital signal processing (DSP) chip and adopt a frequency domain based algorithm for the computation of power elements. The measurement system is expected to offer both high speed and accuracy, and can show wide spectra limited only by the sampling frequency.

In recent years, the worldwide progress of wireless communication technology has bringing great benefit and convenience to our people¡¦s life. Nowadays, people can use appliances of wireless communication in many fields, such as family-monitoring, automatic system, and smart-type device¡Ketc. However, in order to dealing with the need of low cost and low power communication, the researcher spend many years on developing the specification of IEEE 802.15.4 Low Rate-Wireless Personal Area Network (LR-WPAN) expected be applied in widespread use. In this thesis, we focus on the baseband signal processing for the physical layer specification of the 868/915MHz mode of the IEEE 802.15.4 LR-WPAN. Our design blocks include packet detection, sampling point detection (energy detection), carrier frequency offset (CFO) compensation, carrier phase offset (CPO) compensation, and despreading algorithms. During the process of simulation, we¡¦ll examine whether our design match the criteria of standard such as sensitivity, packet format, and modulation. While our designs achieve the requirement of the standard, we start on quantization. Finally, we¡¦ll realize the algorithm in VHDL and examine it.

Thesis (M.S.)--California Polytechnic State University, 2009. / Mode of access: Internet. Title from PDF title page; viewed on December 1, 2009. Major professor: Dr. Lily Laiho. "Presented to the faculty of California Polytechnic State University, San Luis Obispo, California." "In partial fulfillment of the requirements for the degree of Master of Science in Biomedical Engineering." "June 2009." Includes bibliographical references (p. 29-30).

Thesis (Ph. D.)--Lehigh University, 2000. / Includes vita. Includes bibliographical references (leaves 135-142).

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 104-108). Available also in a digital version from Dissertation Abstracts.

Thesis (Ph. D.)--University of Hong Kong, 2001. / Includes bibliographical references.