The characteristics of a silicon-on-insulator (SOI) rib waveguide, including the bending loss of a multimode bent waveguide and the birefringence of a rib waveguide, are analyzed by using a finite-difference method (FDM). Based on a detailed analysis for a multimode bent waveguide, an appropriately designed multimode bent waveguide for reducing effectively the bending loss of the fundamental mode is realized. The slab height and the rib width of an SOI rib waveguide are normalized with the total height of the silicon layer and a general relation between these two normalized parameters for a nonbirefringent SOI rib waveguide is established. Using this general relation, one can easily design a nonbirefringent SOI rib waveguide. The issue of multimode effect in the SOI-based microphotonic devices such as arrayed-waveguide gratings (AWGs), etched diffraction gratings (EDGs), and multimode interference (MMI) couplers is discussed in detail. Two kinds of taper structures are proposed for reducing the multimode effects in EDGs or MMI couplers. A bi-level taper is introduced to eliminate effectively the multimode effects in an EDG or an MMI coupler. The bi-level taper is very appropriate for an EDG demultiplexer since the Si layer is etched through simultaneously for both the grating and the bottom taper structure, and thus no additional fabrication process is required. For the simulation of an AWG demultiplexer, a fast simulation method based on the Gaussian approximation is proposed and two kinds of effective and accurate three-dimensional (3D) simulation modeling are developed. The first 3D model is based on Kirchhoff-Huygens diffraction formula. To improve the computational speed, the 3D model is reduced to a two-dimensional (2D) one by integrating the corresponding field distributions in the AWG demultiplexer along the vertical direction under an assumption that the power coupled to the higher order modes in the free propagation region (FPR) is negligibly small. The equivalent 2D model has an almost the same accuracy as the original 3D model. Furthermore, a reciprocity theory is introduced for the optimal designof a special structure used for flattening the spectral response of an AWG demultiplexer. In the second 3D simulation method, we combine a beam propagation method (BPM) and the Kirchhoff-Huygens diffraction formula. In this method, a 3D BPM in a polar coordinate system is used for calculating the light propagation in the region connecting the first FPR and the arrayed waveguides, and thus the coupling coefficient of each arrayed waveguide is calculated conveniently and accurately. In the simulation of the second FPR, due to the uniform arrangement of arrayed waveguides, only several arrayed waveguides are needed in the BPM window and thus the computational efficiency is improved. / QC 20101004

abstract: Combining the rapid development of semiconductor technologies, miniaturization of integrated circuits (ICs), and scaling down the device size is trending towards faster, cheaper, and more reliable components for low-power integrated circuits. Most research and development relate to efficiency, structure, materials, and performance. However, the thermal problem is also created and becomes more critical with shrinking device dimensions and increased integration densities, such that it affects the device performance and leads to degradation and damage. At the nanometer scale, the self-heating effect (SHE) is one of the main factors to degrade devices. Therefore, tracking and quantifying the SHE is important for reliability and efficiency issues. In this dissertation, engineers design two identical and closely spaced 40nm gate length silicon-on-insulator (SOI) n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) that share a common source with the same active silicon region. One of the MOSFETs acts as a heater to heat-up the active region, while the other one is a thermometer to evaluate the SHE and local temperature changes. The thermometer provides a method to calibrate the numerical models of self-heating and track the heat flow. Moreover, it also involves a trap-rich SOI wafer technology, in which a trap-rich layer, with higher resistivity and lower thermal conductivity compared to conventional bulk silicon substrates. The trap-rich SOI substrates can reduce the cross-talk and minimize the power consumption to increase the system performance. In particular, it offers a solution to radio frequency integrated circuits (RFICs) which require fast switching and low leakage. In high power amplifier (PA) applications, Watt-level PAs operates at less than 50% efficiency because of temperature limitations. The author uses experimental measurements of the local temperature changes, combined with simulations to examine the heat flow and temperature distribution. The approach may be useful to build a self-test application, because it can quantify the temperature changes by putting one or multiple NMOSFET thermometers around a complementary metal-oxide-semiconductor (CMOS) power amplifier, while only adding minimum die area. It points to ways in which it can optimize the reliability of RFIC applications, which operate under high-temperature or high-power conditions to protect the device before it is overheated or damaged. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

The semiconductor industry scaling has mainly been driven by Moore's law, which states that the number of transistors on a single chip should double every year and a half to two years. Beyond 2011, when the channel length of the Metal Oxide Field effect transistor (MOSFET) approaches 16 nm, the scaling of the planar MOSFET is predicted to reach its limit. Consequently, a departure from the current planar MOSFET on bulk silicon substrate is required to push the scaling limit further while maintaining electrostatic control of the gate over the channel. Alternative device structures that allow better control of the gate over the channel such as reducing short channel effects, and minimizing second order effects are currently being investigated. Such novel device architectures such as Fully-Depleted (FD) planar Silicon On Insulator (SOI) MOSFETS, Triple gate SOI MOSFET and Gate-All-Around Nanowire (NW) MOSFET utilize Silicon on Insulator (SOI) substrates to benefit from the bulk isolation and reduce second order effects due to parasitic effects from the bulk. The doping of the source and drain regions and the redistribution of the dopants in the channel greatly impact the electrical characteristics of the fabricated device. Thus, in nano-scale and reduced dimension transistors, a tight control of doping levels and formation of pn junctions is required. Therefore, deeper understanding of the lateral component of the diffusion mechanisms and interface effects in these lower dimensional structures compared to the bulk is necessary. This work focuses on studying the dopant diffusion mechanisms in Silicon nanomembranes (2D), nanoribbons (â 1.Xâ D), and nanowires (1D). This study also attempts to benchmark the 1D and 2D diffusion against the well-known bulk (3D) diffusion mechanisms. / Master of Science

La technologie Smart Cut™ est un procédé générique de transfert de couches minces utilisé pour la fabrication des substrats silicium sur isolant (SOI) à l’échelle industrielle. L’implantation d’ions légers dans un substrat de silicium oxydé mène à la formation d’une zone fragilisée enterrée au sein du cristal. Ce substrat implanté est ensuite solidarisé à un support mécanique grâce à la technique de collage par adhésion moléculaire. Sous l’effet de la température, les espèces implantées évoluent sous la forme de microfissures qui se développent de manière parallèle à la surface. Après recuit, une fracture se déclenche au niveau de la zone implantée et permet le report de la fine couche monocristalline. L’objet de cette thèse est d’étudier l’aspect dynamique de cette étape de fracture.Pour ce faire, la vitesse de rupture et la déformation des plaques à l’arrière du front de fracture ont tout d’abord été mesurées à l’aide d’un montage optique original qui a ensuite été étendu aux études sur plaque entière 300mm. Ces données ont ensuite été modélisées. Dans un deuxième temps, l’interaction entre le front de fracture et des ondes acoustiques émises dynamiquement au cours de sa propagation a été étudiée. Celle-ci conduit à l’apparition récurrente d’un motif périodique sur le faciès de rupture qui consiste en une très faible variation de rugosité sur de très grandes périodes (mm). Des mesures expérimentales permettent tout d’abord de mettre en évidence cette émission acoustique et d’étudier ses caractéristiques. La modélisation physique du phénomène puis sa simulation numérique permettent ensuite de retrouver la forme typique de ce motif. Enfin, des solutions technologiques sont proposées pour empêcher son apparition sur le faciès de rupture des plaques SOI. / The Smart Cut™ technology is a generic way of transferring very thin layers of crystalline material onto a mechanical substrate. It is currently the industrial standard for Silicon On Insulator (SOI) manufacturing. The implantation of relatively high doses of gas ions in a thermally oxidized silicon substrate leads to the formation of a buried weakened layer in the crystal. The implanted wafer is then bonded onto a host substrate using direct wafer bonding. Under annealing, the implanted species evolve into microcracks lying parallel to the surface, and a controlled fracture process finally occurs along the implanted layer. The aim of this thesis is to study the dynamics of this fracture step.First of all, the fracture velocity and the deformation profile behind the crack tip have been measured using an original optical setup, which has been extended to full wafer studies. A model has been established to explain these data. Then, the interaction of the fracture front with self-generated acoustic waves has been studied. This interaction leads to the appearance of a macroscopic periodic pattern on post-split SOI wafers which is made of small variations of the SOI roughness on very large periods (mm). Experimental studies are first carried out to look at the fracture acoustic emission for different experimental conditions. Numerical simulations based on acoustic phase calculations are then performed to recover the typical pattern shape, with results consistent with experimental data. Finally, technologic solutions are proposed to prevent the pattern formation on the post-split SOI wafers.

Polarization dependences of optical devices in highly-integrated optical systems become a major problem. To overcome this issue, one can implement polarization diversity scheme to achieve a single polarization on-chip network. One of the essential components in a polarization diversity scheme is the polarization beam splitter (PBS). In this thesis, we will a PBS based on a silicon-on-insulator (SOI) platform with reduced device size and broad operation bandwidth. We use the three-dimensional Finite-Difference Time-Domain (3D-FDTD) method to perform the simulation. First, we use two asymmetric waveguides to design an asymmetric directional coupler with only TE-like mode phase matching condition. We then tape the lower waveguide to keep the TE-polarized light, and split the TE- and TM- polarized light. By utilizing an asymmetrical directional coupler with a tapered waveguide, we have achieved a 7.3

À la base de l’évolution de la technologie microélectronique actuelle, la réduction des dimensions critiques des MOSFET standards pour améliorer leurs performances électriques a atteint depuis quelques années ses limites physiques. L’utilisation de nanocomposants innovateurs ayant une configuration planaire, comme solution de remplacement, semble être une voie prometteuse pour certaines applications. Les diodes autocommutantes, Self-Switching Diodes (SSD), en font partie. Les SSD sont des composants unipolaires à deux accès ayant une caractéristique I-V non-linéaire semblable à celle d’une diode bipolaire. Leur configuration planaire rend leur fabrication plus facile et réduit considérablement les capacités parasites intrinsèques. Cette thèse porte sur la fabrication, la simulation et la caractérisation électrique de SSD fabriquées sur des substrats en SOI (Silicon-On-Insulator). Les dispositifs SSD ont été réalisés au départ grâce à des gravures par FIB (Focussed Ion Beam). Cette technique polyvalente nous permet de contrôler en temps réel les conditions de gravure. Par la suite, nous avons procédé à une fabrication massive de SSD en utilisant la technique d’électrolithographie et de gravure sèche. Les simulations effectuées principalement avec TCAD-Medici nous ont permis d’optimiser et d’investiguer en détails l’effet critique des paramètres géométriques (longueur, largeur et épaisseur du canal conducteur ainsi que la largeur des tranchées isolantes) et des paramètres physiques (densité surfacique aux niveaux des interfaces isolant/semiconducteur, densité des dopants et type de diélectrique dans les tranchées isolantes) des SSD sur les caractéristiques électriques, les valeurs de la tension seuil et les phénomènes de transport non linéaire qui ont lieu dans le canal conducteur de ce type de composants. Les mesures expérimentales de caractéristiques I-V de SSD ayant des canaux conducteurs de largeurs et de longueurs variables confirment les prévisions de nos simulations. Bien que le comportement électrique des SSD ressemble à celui d’un MISFET, nous démontrons le fait que l’on ne peut modéliser leurs caractéristiques I-V avec les mêmes expressions en nous basant sur le principe de fonctionnement spécifique à chacun de ces deux dispositifs.

Ce travail de thèse est consacré à l’étude expérimentale des mécanismes de démouillage de films solides d’épaisseur nanométrique conduisant à la transformation d’un film mince en une assemblée d’îlots tridimensionnels. L’utilisation de la microscopie à électrons lents (LEEM) nous a permis d’étudier la morphologie et la cinétique in situ et en temps réel du démouillage de films de Si/SiO2 (SOI) et de Ge/SiO2 (GOI) obtenus par collage moléculaire (procédé Smart Cut™). Ces mesures expérimentales ont été complétées par des analyses par diffusion centrale des rayons X en incidence rasante (GISAXS) et des observations ex situ par microscopie à force atomique (AFM). Les mécanismes de démouillage de SOI et GOI sont thermodynamiquement pilotés par la capillarité et cinétiquement contrôlés par la diffusion de surface. L’étude complémentaire du démouillage à partir de fronts cristallographiquement orientés obtenus par lithographie nous a permis d’analyser le rôle central du facettage, de l’anisotropie cristalline et des processus de formation du bourrelet de démouillage. En particulier, le rôle de la nucléation 2D sur la cinétique d’épaississement (couche par couche) du bourrelet a pu être mis en évidence. Les résultats expérimentaux ont pu être confrontés à des modèles analytiques et des simulations de type Monte Carlo cinétique. Nous en avons déduit les valeurs des paramètres physiques pertinents et avons attribué les différences de morphologies entre SOI et GOI à la présence de facettes spécifiques. / This work is devoted to the experimental study of the dewetting mechanisms of ultrathin solid films by which a metastable film transforms into an assembly of tridimensional crystallites. Using low energy Electron Microscopy (LEEM) we analyse, in situ and in real time, the morphology and the kinetics of the dewetting of Si/SiO2 (SOI) and Ge/SiO2 (GOI) systems obtained by molecular bonding (Smart Cut™ process). Further information has been obtained by Grazing Incidence Small Angle X–ray Scattering (GISAXS) and Atomic Force Microscopy (AFM) measurements. We show that the dewetting is driven by surface free energy minimization and mediated by surface diffusion. A complementary study of artificial well-oriented dewetting fronts obtained by lithography enables us to analyze the important role played by facets, the crystal anisotropy and the rim thickening mechanism. We show that the rim thickening proceeds in a layer-by-layer mode and is limited by 2D nucleation. Thanks to analytical models and Kinetics Monte Carlo simulations, numerical values of the pertinent physical parameters involved in the dewetting process are obtained and the morphological differences between SOI and GOI are attributed to the presence of specific facets.

Cette thèse s’intéresse à une technique de caractérisation particulièrement bien adaptée à l’étude de couches diélectriques ultra-minces sur semiconducteurs. La génération de seconde harmonique (SHG) est une méthode très prometteuse, basée sur l’optique non-linéaire. Un laser est focalisé sur l'échantillon à caractériser et le signal à deux fois la fréquence fondamentale est mesuré. Pour les matériaux centrosymétriques comme c-Si, SiO2 et Al2O3, le signal SHG est dû aux défauts et au champ électrique Edc d’interface (induit par les charges préexistantes Qox et/ou piégées au niveau des pièges d’interface Dit). La SHG donne ainsi accès à la qualité des interfaces entre diélectriques/semiconducteurs. Néanmoins, le signal SHG dépend aussi des phénomènes de propagation optique dans les structures multicouches. Pour cette raison, nous avons développé un programme de simulation qui prend en compte les phénomènes optiques et les champs électriques statiques aux interfaces. Nous avons utilisé la SHG pour analyser la qualité de passivation de structures Al2O3/Si préparées avec des procédés différents et nous avons montré une corrélation entre SHG et mesure de durée de vie des porteurs de charges. Les valeurs de Qox et Dit ont été extraites par des mesures de capacité-tension et elles ont permis de calculer le champ Edc. La simulation optique, avec les valeurs extraites de Edc a permis de reproduire les données expérimentales de SHG dans ces structures. La SHG a été utilisée également pour la caractérisation des substrats Silicium-sur-Isolant (SOI). Pour les structures SOI épaisses, la simulation et les résultats expérimentaux ont montré que la réponse SHG est dominée par les interférences optiques (faible impact de Edc). Pour les structures SOI ultraminces, les interfaces sont couplées électriquement et des valeurs de Edc sont nécessaires pour reproduire les données expérimentales par simulation. Cela implique que pour les SOI ultraminces, la SHG pourrait donner accès aux champs électriques au niveau des interfaces d’une manière non-destructive. / This PhD work was developed in the context of research for novel characterization methods for ultra-thin dielectric films on semiconductors and their interfacial quality. Second harmonic generation (SHG) is a very promising non-invasive technique based on nonlinear optics. A laser emitting at the fundamental frequency is incident upon the sample which responds through its 2nd order polarization, generating a signal at twice the fundamental frequency. For centrosymmetric materials such as c-Si, amorphous SiO2 or Al2O3, the SHG signal is mainly due to the defects and to the static electric field Edc present at the interface (due to pre-existing charges Qox and/or photo-injected charge trapping/detrapping at interface traps Dit). Thus, SHG measurement gives access to the quality of dielectric/semiconductor interfaces. Nevertheless, the SHG signal is also dependent on multilayer optical propagation phenomena. For this reason, we have developed a simulation program which accounts for the optical phenomena and the static electric fields at the interfaces. We have used SHG to monitor the passivation quality of Al2O3/Si structures prepared with different processes and showed a correlation between SHG and minority carrier lifetime measurements. Qox and Dit were extracted from capacitance-voltage measurements and helped calculating the Edc values. The optical simulation, fed with known Edc values reproduced the experimental SHG data in these structures. The SHG was also used for Silicon-on-Insulator (SOI) substrates characterization. In thick SOI structures, both simulations and experimental results show that the SHG response is mainly given by optical interferences (Edc has no impact). In ultrathin SOI, the interfaces are electrically coupled and Edc is needed as input in the simulation in order to reproduce the experimental SHG data. This implies that in ultrathin SOI, SHG can access the interface electric fields in a non-destructive way.

Accelerometer sensors fabricated with micromachining technologies started to take place of yesterday&rsquo / s bulky sensors in many application areas. The application areas include a wide range from consumer electronics and health systems to military and aerospace applications. Therefore, the performance requirements extend form 1 &mu / g&rsquo / s to 100 thousand g&rsquo / s. However, high performance strategic grade MEMS accelerometer sensors still do not exist in the literature. Smart designs utilizing the MEMS technology is necessary in order to acquire high performance specifications. This thesis reports a high performance accelerometer with a new process by making the use of bulk micromachining technology. The new process includes the utilization of Silicon-on-Insulator (SOI) wafer and its buried oxide (BOX) layer. The BOX layer helps to realize interdigitated finger structures, which commonly find place in surface micromachined CMOS-MEMS capacitive accelerometers. The multi-metal layered CMOS-MEMS devices inherently incorporate interdigitated finger structures. Interdigitated finger structures are highly sensitive to acceleration in comparison with comb-finger structures, which generally find usage in bulk-micromachined devices, due to absence of anti-gap. The designed sensors based on this fabrication process is sought to form a fully-differential signal interfaced sensor with incorporation of the advantages of high sensitive interdigitated finger electrodes and high aspect ratio SOI wafer&rsquo / s bulk single crystal silicon device. Under the light of the envisaged process, sensor designs were made, and verified using a computing environment, MATLAB, and a finite element analysis simulator, CoventorWARE. The verified two designs were fabricated, and all the tests, except the centrifuge test, were made at METU-MEMS Research Center. Among the fabricated sensors, the one designed for the high performance achieves a capacitance sensitivity of 178 fF with a rest capacitance of 8.1 pF by employing interdigitated finger electrodes, while its comb-finger implementation can only achieve a capacitance sensitivity of 75 fF with a rest capacitance of 10 pF.

Integrated Silicon Photonics has emerged as a powerful platform in the last two decades amongst high-bandwidth technologies, particularly since the adop- tion of CMOS compatible silicon-on-insulator(SOI) substrates. Microring res- onators are one of the fundamental blocks on a photonic integrated circuit chip o ering versatility in varied applications like sensing, optical bu ering, ltering, loss measurements, lasing, nonlinear e ects, understanding cavity optomechanics etc. This thesis covers the design and modeling of microring resonators for biosensing applications. The two applications considered are : homogeneous biosensing and wrist pulse pressure monitoring. Also, the designs have been used to fabricate ring resonator device using three different techniques. The results obtained through characterization of these devices are presented. Following are the observations made in lieu of this: 1) Design modeling and analysis - The analysis of ring resonator requires the study of both the straight and bent waveguide sections. Both rib and strip waveguide geometries have been considered for constructing the device as a building block by computing their respective eigen modes for both quasi-TE and quasi-TM polarizations. The non-uniform evanescent coupling between the straight and curved waveguide has been estimated using coupled mode theory. This method provided in estimating the quality-factor and free spec- tral range (FSR) of the ring-resonator. A case for optimizing the waveguide gap in the directional coupler section of a ring resonator has been presented for homogeneous biosensing application. On similar lines, a model of applying ring resonator for arterial pulse-pressure measurement has been analyzed. The results have been obtained by employing FD-BPM and FDTD including semi- vectorial eigen mode solutions to evaluate the spectral characteristics of ring resonator. The modeling and analytical results are supported by commercial software tools (RSoft). 2) Fabrication and Characterization - For the fabrication, we employ the design of ring resonator of radius 20 m on SOI substrate with two different waveguide gaps of 350 and 700 nm. Three different process sows have been used for fabricating the same device. The rst technique involved using negative e-beam resist HSQ which after exposure becomes SiO2, acts as a mask for Reactive-Ion Etching (RIE); helping in eliminating an additional step. The second technique involved the use of positive e-beam resist, PMMA for device patterning followed by metal deposition with lift-o . The third tech- nique employed was Focussed Ion-beam (FIB) which is resist-less patterning by bombarding Ga+ ions directly onto the top surface of the wafer with the help of a GDS le. The characterization process involved estimation of loss and observing the be- havior of optical elds in the device around the wavelength of 1550 nm using near-field scanning optical microscopy (NSOM) measurement. The estimation of roughness-induced losses has been made by performing Atomic Force Microscopy (AFM) measurements. In summary, the thesis presents novel design and analysis of SOI based microring resonators for homogeneous biosensing and wrist pulse pressure sensing applications. Also, the fabrication and characterization of 20 m radius ring- resonator with 500 500 nm rib cross-section is presented. Hence, this study brings forth several practical issues concerning application of ring resonators to biosensing applications.