Not available

Silicon-based nanostructures are essential building blocks for nanoelectronic devices and nano-electromechanical systems (NEMS), and their mechanical and electrical properties play an important role in controlling the functionality and reliability of the nano-devices. The objective of this dissertation is twofold: The first is to investigate the mechanical properties of silicon nanolines (SiNLs) with feature size scaled into the tens of nanometer level. And the second is to study the electron transport in nickel silicide formed on the SiNLs. For the first study, a fabrication process was developed to form nanoscale Si lines using an anisotropic wet etching technique. The SiNLs possessed straight and nearly atomically flat sidewalls, almost perfectly rectangular cross sections and highly uniform linewidth at the nanometer scale. To characterize mechanical properties, an atomic force microscope (AFM) based nanoindentation system was employed to investigate three sets of silicon nanolines. The SiNLs had the linewidth ranging from 24 nm to 90 nm, and the aspect ratio (Height/linewidth) from 7 to 18. During indentation, a buckling instability was observed at a critical load, followed by a displacement burst without a load increase, then a fully recoverable deformation upon unloading. For experiments with larger indentation displacements, irrecoverable indentation displacements were observed due to fracture of Si nanolines, with the strain to failure estimated to be from 3.8% to 9.7%. These observations indicated that the buckling behavior of SiNLs depended on the combined effects of load, line geometry, and the friction at contact. This study demonstrated a valuable approach to fabrication of well-defined Si nanoline structures and the application of the nanoindentation method for investigation of their mechanical properties at the nanoscale. For the study of electron transport, a set of nickel monosilicde (NiSi) nanolines with feature size down to 15 nm was fabricated. The linewidth effect on nickel silicide formation has been studied using high-resolution transmission electron microscopy (HRTEM) for microstructural analysis. Four point probe electrical measurements showed that the residual resistivity of the NiSi lines at cryogenic temperature increased with decreasing line width, indicating effect of increased electron sidewall scattering with decreased line width. A mean free path for electron transport at room temperature of 5 nm was deduced, which suggests that nickel silicide can be used without degradation of device performance in nanoscale electronics.

Silicon based 3D fin structure is believed to be the potential future of current semiconductor technology. However, there are significant challenges still exist in realizing a manufacturable fin based process. In this work, we have studied the effects of hydrogen anneal on the structural and electrical characteristics of silicon fin based devices: tri-gate, finFET to name a few. H₂ anneal is shown to play a major role in structural integrity and manufacturability of 3D fin structure which is the most critical feature for these types of devices. Both the temperature and the pressure of H₂ anneal can result in significant alteration of fin height and shape as well as electrical characteristics. Optimum H₂ anneal is required in order to improve carrier mobility and device reliability as shown in this work. A new hard-mask based process was developed to retain H₂ anneal related benefit while eliminating detrimental effects such as reduction of device drive current due to fin height reduction. We have also demonstrated a novel 1T-1C pseudo Static Random Access Memory (1T-1C pseudo SRAM) memory cell using low cost conventional tri-gate process by utilizing selective H₂ anneal and other clever process techniques. TCAD-based simulation was also provided to show its competitive advantage over other types of static and dynamic memories in 45nm and beyond technologies. A high gain bipolar based on silicon fin process flow was proposed for the first time that can be used in BiCMOS technology suitable for low cost mixed signal and RF products. TCAD-based simulation results proved the concept with gain as high 100 for a NPN device using single additional mask. Overall, this work has shown that several novel process techniques and selective use of optimum H₂ anneal can lead to various high performance and low cost devices and memory cells those are much better than the devices using current conventional 3D fin based process techniques. / text