The primary objective of the research project was to further develop a computer program modeling the hydrocracking of partially hydrogenated vacuum gas oil (HVGO), and to use the model to compare the theoretical product distribution to experimental data describing the product distribution of an industrial pilot reactor. The hydrocracking of HVGO on acid zeolites is effectively modeled utilizing a single-event kinetic approach developed by Froment and coworkers. The hydrocracking of HVGO can be described in terms of the fundamental reaction steps involving carbenium ions. Some 45 single-event rate parameters are used to dictate the rate of each single-event in the reaction network. The composition of the partially hydrogenated feed stock is detailed up to C33. Each component and lump is considered in terms of the elementary steps to generate a network of continuity equations and single-event rate parameters. A reactor model comprising this kinetic model can be used to simulate the isothermal and nonisothermal hydrocracking of a HVGO feed stock. The results are represented in terms of the yields of 241 lumps and components in the gas phase and 241 components and lumps in the liquid phase. The predicted yields of various commercial oil fractions and particular components are then compared to experimental data from an industrial pilot reactor to verify the accuracy of the model and the single-event rate parameters.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 77-81).

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.

Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event effects. For digital systems, the transients can upset the logic values in the storage cells which are called single event upsets, or in the combinational logic circuits which are called single event transients. While for analog systems, the transient will introduce noises and change the operating point. The influence becomes more notable in advanced technologies, where devices are more susceptive to the perturbations due to the compact layout. Recently radiation-hardened-by-design has become an effective approach compared to that of modifying semiconductor processes. Hence it is used in this thesis project. Firstly, three elaborately designed radiation-tolerant registers are implemented. Then, two built-in testing circuits are introduced. They are used to detect and count the single event upsets in the registers during high-energy particle tests. The third part is the pulse width measurement circuit, which is designed for measuring the single event transient pulse width in combinational logic circuits. According to the simulations, transient pulse width ranging from 90.6ps to 2.53ns can be effectively measured. Finally, two frequently used cross-coupled LC tank voltage-controlled oscillators are studied to compare their radiation tolerances. Simulation results show that the direct power connection and transistors working in the deep saturation mode have positive influence toward the radiation tolerance. All of the circuit designs, simulations and analyses are based on STMicroelectronics CMOS 90 nm 7M2T General Process.

Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively.

In this work, the reaction scheme of the MTO process was written in terms of elementary steps and generated by means of a computer algorithm characterizing the various species by vectors and Boolean relation matrices. The number of rate parameters is very large. To reduce this number the rate parameters related to the steps on the acid sites of the catalyst were modeled in terms of transition state theory and statistical thermodynamics. Use was made of the single event concept to account for the effect of structure of reactant and activated complex on the frequency factor of the rate coefficient of an elementary step. The Evans-Polanyi relation was also utilized to account for the effect of the structure on the change in enthalpy. The structure was determined by means of quantum chemical software. The number of rate parameters of the complete reaction scheme to be determined from experimental data is thus reduced from 726 to 30. Their values were obtained from the experimental data of Abraha by means of a genetic algorithm involving the Levenberg-Marquardt algorithm and combined with sequential quadratic programming. The retained model yields an excellent fit of the experimental data. All the parameters satisfy the statistical tests as well as the rules of carbenium ion chemistry. The kinetic model also reproduces the experimental data of Marchi and Froment, also obtained on SAPO-34. Another set of their data was used to introduce the deactivation of the catalyst into the kinetic equations. This detailed kinetic model was used to investigate the influence of the operating conditions on the product distribution in a multi-bed adiabatic reactor with plug flow. It was further inserted into riser and fluidized bed reactor models to study the conceptual design of an MTO reactor, accounting for the strong exothermicity of the process. Multi-bed adiabatic and fluidized bed technologies show good potential for the industrial process for the conversion of methanol into olefins.

In this work, a fundamental kinetic model for the catalytic reforming process has been developed. The complex network of elementary steps and molecular reactions occurring in catalytic reforming has been generated through a computer algorithm characterizing the various species by vectors and Boolean relation matrices. The algorithm is based on the fundamental chemistry occurring on both acid and metal sites of the catalyst. Rates are expressed for each of the elementary steps involved in the transformation of the intermediates. The Hougen-Watson approach is used to express the rates of the molecular reactions occurring on the metal sites of the catalyst. The single event approach is used to account for the effect of structure of reactant and activated complex on the rate coefficients of the elementary steps occurring on the acid sites. This approach recognizes that even if the number of elementary steps is very large they belong to a very limited number of types, and therefore it is possible to express the kinetics of elementary steps by a reduced number of parameters. In addition, the single event approach leads to rate coefficients that are independent of the feedstock, due to their fundamental chemical nature. The total number of parameters at isothermal conditions is 45. To estimate these parameters, an objective function based upon the sum of squares of the residuals was minimized through the Marquardt algorithm. Intraparticle mass transport limitations and deactivation of the catalyst by coke formation are considered in the model. Both the Wilke and the Stefan-Maxwell approaches were used to calculate the concentration gradients inside of the particle. The heterogeneous kinetic model was applied in the simulation of the process for typical industrial conditions for both axial and radial flow fixed bed reactors. The influence of the main process variables on the octane number and reformate volume was investigated and optimal conditions were obtained. Additional aspects studied with the kinetic model are the reduction of aromatics, mainly benzene. The results from the simulations agree with the typical performance found in the industrial process.

L’environnement radiatif spatial est particulièrement critique pour la fiabilité des circuits intégrés et systèmes électroniques embarqués. Cet environnement chargé en particules énergétiques (proton, électron, ions lourds, etc) peut conduire à des pannes transitoires (SET), ou permanentes (SEU) et dans certains cas destructives (type Latchup, SEL) dans les dispositifs embarqués. L'effet d'une seule particule est identifié comme un événement singulier (SEE). Les contraintes imposées par l'intégration technologique poussent les fabricants micro-électroniques à prendre en considération la vulnérabilité de leurs composants vis-à-vis du Latchup tout en considérant les phénomènes non destructifs tels que la corruption de données (SEU/MBU). Cette thèse est le fruit d'une collaboration entre l'ONERA et Sofradir, fabriquant électronique d'imageurs infrarouge. L'objectif de cette thèse est d'étudier les effets singuliers (SET/SEU/SEL) de la technologie CMOS utilisée par Sofradir dans des conditions de températures cryogéniques, et plus particulièrement l'effet Latchup. / The spatial radiative environment is particularly critical for the reliability of integrated circuits and embedded electronic systems. This environment loaded with energetic particles (proton, electron, heavy ions, etc.) can lead to transient (SET), or permanent (SEU) and insome cases destructive failures (Latchup, SEL) in embedded devices. The effect of a single particle is identified as a single event effect(SEE). The constraints imposed by technological integration push microelectronics manufacturers to consider the vulnerability of their components to Latchup while consideringnon-destructive phenomena such as data corruption (SEU/MBU). This thesis is the result ofcollaboration between ONERA and Sofradir, an electronic manufacturer of infrared imagers. The aim of this thesis is to study the singular effects (SET / SEU / SEL) of the CMOS technology used by Sofradir under cryogenic temperature conditions, and more particularly the Latchup effect.

Neural Networks have proven themselves very adept at solving a wide variety of problems, in particular they accel at image processing. However, it remains unknown how well they perform under memory errors. This thesis focuses on the robustness of neural networks under memory errors, specifically single event upset style errors where single bits flip in a network's trained parameters. The main goal of these experiments is to determine if different neural network architectures are more robust than others. Initial experiments show that MLPs are more robust than CNNs. Within MLPs, deeper MLPs are more robust and for CNNs larger kernels are more robust. Additionally, the CNNs displayed bimodal failure behavior, where memory errors would either not affect the performance of the network, or they would degrade its performance to be on par with random guessing. VGG16, ResNet50, and InceptionV3 were also tested for their robustness. ResNet50 and InceptionV3 were both more robust than VGG16. This could be due to their use of Batch Normalization or the fact that ResNet50 and InceptionV3 both use shortcut connections in their hidden layers. After determining which networks were most robust, some estimated error rates from neutrons were calculated for space environments to determine if these architectures were robust enough to survive. It was determined that large MLPs, ResNet50, and InceptionV3 could survive in Low Earth Orbit on commercial memory technology and only use software error correction. / Master of Science / Neural networks are a new kind of algorithm that are revolutionizing the field of computer vision. Neural networks can be used to detect and classify objects in pictures or videos with accuracy on par with human performance. Neural networks achieve such good performance after a long training process during which many parameters are adjusted until the network can correctly identify objects such as cats, dogs, trucks, and more. These trained parameters are then stored in a computers memory and then recalled whenever the neural network is used for a computer vision task. Some computer vision tasks are safety critical, such as a self-driving car’s pedestrian detector. An error in that detector could lead to loss of life, so neural networks must be robust against a wide variety of errors. This thesis will focus on a specific kind of error: bit flips in the parameters of a neural networks stored in a computer’s memory. The main goal of these bit flip experiments is to determine if certain kinds of neural networks are more robust than others. Initial experiments show that MLP (Multilayer Perceptions) style networks are more robust than CNNs (Convolutional Neural Network). For MLP style networks, making the network deeper with more layers increases the accuracy and the robustness of the network. However, for the CNNs increasing the depth only increased the accuracy, not the robustness. The robustness of the CNNs displayed an interesting trend of bimodal failure behavior, where memory errors would either not affect the performance of the network, or they would degrade its performance to be on par with random guessing. A second set of experiments were run to focus more on CNN robustness because CNNs are much more capable than MLPs. The second set of experiments focused on the robustness of VGG16, ResNet50, and InceptionV3. These CNNs are all very large and have very good performance on real world datasets such as ImageNet. Bit flip experiments showed that ResNet50 and InceptionV3 were both more robust than VGG16. This could be due to their use of Batch Normalization or the fact that ResNet50 and InceptionV3 both use shortcut connections within their network architecture. However, all three networks still displayed the bimodal failure mode seen previously. After determining which networks were most robust, some estimated error rates were calculated for a real world environment. The chosen environment was the space environment because it naturally causes a high amount of bit flips in memory, so if NASA were to use neural networks on any rovers they would need to make sure the neural networks are robust enough to survive. It was determined that large MLPs, ResNet50, and InceptionV3 could survive in Low Earth Orbit on commercial memory technology and only use software error correction. Using only software error correction will allow satellite makers to build more advanced satellites without paying extra money for radiation-hardened electronics.

Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude. / This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.