Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude. / This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.

Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude. / This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.

Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e células de memória 6T SRAM feitas com estes dispositivos. Para conseguir isso, foram usadas ferramentas TCAD para simular falhas transientes devido a impacto de íons pesados a nível dispositivo e nível circuito. As simulações neste ambiente tem como vantagem a simulação dos fatos e mecanismos que produz as falhas transientes e seus efeitos nos dispositivos, além de também servir para projetar virtualmente estes dispositivos e caraterizar eles para estas simulações. Neste caso, foram projetados três dispositivos para simulação: um transistor NMOS de 32nm Bulk, um transistor NMOS de 28nm FDSOI e um transistor NMOS de 28nm FDSOI High-K para fazer comparações entre eles. Estes dispositivos foram projetados, caraterizados e testados contra o impacto de íons pesados a níveis dispositivo e circuito. Como resultado obtido, transistor Bulk de 32nm teve, no pior caso, uma carga coletada de 7.57 e 7.19 vezes maior que a carga coletada pelo dispositivo FDSOI de 28nm e FDSOI High-K de 28nm respectivamente atingido pelo mesmo íon pesado de 100MeV-cm2/mg. Com estes dados foi possível modelar o comportamento da carga coletada de ambos dispositivos usando este íon pesado, atingindo os terminais de Fonte e Dreno em distintos lugares e ângulos. Usando a mesma ferramenta e os dados obtidos de carga coletada pelos testes anteriores, foram projetadas células de memória SRAM de 6 transistores. Isso foi para testar elas contra os efeitos do impacto de íons pesados nos transistores NMOS de armazenagem da dados. Neste caso, a Transferência Linear de Energia (LET) do íon necessária para fazer que o dado armazenado na SRAM Bulk mude é 12.8 vezes maior que no caso da SRAM FDSOI e 10 maior no caso da SRAM FDSOI High-K, embora a quantidade de carga coletada necessária para que o dado mude em ambas células seja quase a mesma. Com estes dados foi possível modelar os efeitos dos íons pesados em ambos circuitos, descobrir a Carga Crítica destes e qual é o mínimo LET necessário para que o dado armazenado nestas SRAMs mude. / This work shows a comparison of faults due to Single-Event Effects in 28nm Fully Depleted SOI (FDSOI), 28nm FDSOI High-K and 32nm Bulk CMOS devices, and in 6T SRAM memory cells made with these devices. To provide this, was used TCAD tools to simulate transient faults due to heavy ion impacts on device and circuit levels. The simulations in that environment have the advantage to simulate the facts and mechanisms which produce the transient faults and this effects on the electronic devices, it also allow to simulate the virtual device fabrication and to characterize them. In this case, two devices were created for the simulations: a 32nm Bulk NMOS transistor and a 28nm FDSOI NMOS transistor for compare them. These devices were created, characterized and tested against heavy ion impacts at device and circuit levels. The results show that 32nm Bulk transistor has, in the worst case, a collected charge 7.57 and 7.19 times greater than the 28nm FDSOI and 28nm FDSOI High-K respectively collected charge with the same 100MeV-cm2/mg heavy ion. With these data it was possible to model the behavior of the collected charge in both devices with the same heavy-ion, reach the Source and Drain Terminal in different places and angles. Using the same tools and the obtained collected charge data of previous simulations, it was designed 6 transistors SRAM Memory Cells. That is done to test these circuits against the heavy ion effects on the data-storage NMOS transistor. In this case, the necessary Ion Linear Energy Transfer (LET) to flip the Bulk SRAM is 12.8 greater than the FDSOI SRAM and 10 times greater than the FDSOI High- K SRAM case, although the amount of charge to flip the cells is almost the same in both cases. With these data it was possible to model the heavy-ion effects in both circuits, discover the Critical Charge of them and the minimum LET to flips these SRAMs.

The growing interest in high speed and RF technologies assert for the importance of reliability characterization beyond the conventional DC methodology. In this work, the influence of bias temperature instability (BTI) stress on RF small signal parameters is shown. The correlation between degradation of DC and RF parameters is established which enables the empirical modelling of stress induced changes. Furthermore, S-Parameters characterization is demonstrated as the tool to qualitatively distinguish between HCI and BTI degradation mechanisms with the help of extracted small signal gate capacitances.

L’émergence des circuits complexes numériques, ou System-On-Chip (SOC), pose notamment la problématique de la consommation énergétique. Parmi les blocs fonctionnels significatifs à ce titre, apparaissent les mémoires et en particulier les mémoires statiques (SRAM). La maîtrise de la consommation énergétique d’une mémoire SRAM inclue la capacité à rendre la mémoire fonctionnelle sous très faible tension d’alimentation, avec un objectif agressif de 300 mV (inférieur à la tension de seuil des transistors standard CMOS). Dans ce contexte, les travaux de thèse ont concerné la proposition d’un point mémoire SRAM suffisamment performant sous très faible tension d’alimentation et pour les nœuds technologiques avancés (CMOS bulk 28nm et FDSOI 28nm). Une analyse comparative des architectures proposées dans l’état de l’art a permis d’élaborer deux points mémoire à 10 transistors avec de très faibles impacts de courant de fuite. Outre une segmentation des ports de lecture, les propositions reposent sur l’utilisation de périphéries adaptées synchrones avec notamment une solution nouvelle de réplication, un amplificateur de lecture de données en mode tension et l’utilisation d’une polarisation dynamique arrière du caisson SOI (Body Bias). Des validations expérimentales s’appuient sur des circuits en technologies avancées. Enfin, une mémoire complète de 32kb (1024x32) a été soumise à fabrication en 28 FDSOI. Ce circuit embarque une solution de test (BIST) capable de fonctionner sous 300mV d’alimentation. Après une introduction générale, le 2ème chapitre du manuscrit décrit l’état de l’art. Le chapitre 3 présente les nouveaux points mémoire. Le 4ème chapitre décrit l’amplificateur de lecture avec la solution de réplication. Le chapitre 5 présente l’architecture d’une mémoire ultra basse tension ainsi que le circuit de test embarqué. Les travaux ont donné lieu au dépôt de 4 propositions de brevet, deux conférences internationales, un article de journal international est accepté et un autre vient d’être soumis. / Emergence of large Systems-On-Chip introduces the challenge of power management. Of the various embedded blocks, static random access memories (SRAM) constitute the angrier contributors to power consumption. Scaling down the power supply is one way to act positively on power consumption. One aggressive target is to enable the operation of SRAMs at Ultra-Low-Voltage, i.e. as low as 300 mV (lower than the threshold voltage of standard CMOS transistors). The present work concerned the proposal of SRAM bitcells able to operate at ULV and for advanced technology nodes (either CMOS bulk 28 nm or FDSOI 28 nm). The benchmarking of published architectures as state-of-the-art has led to propose two flavors of 10-transitor bitcells, solving the limitations due to leakage current and parasitic power consumption. Segmented read-ports have been used along with the required synchronous peripheral circuitry including original replica assistance, a dedicated unbalanced sense amplifier for ULV operation and dynamic forward back-biasing of SOI boxes. Experimental test chips are provided in previously mentioned technologies. A complete memory cut of 32 kbits (1024x32) has been designed with an embedded BIST block, able to operate at ULV. After a general introduction, the manuscript proposes the state-of-the-art in chapter two. The new 10T bitcells are presented in chapter 3. The sense amplifier along with the replica assistance is the core of chapter 4. The memory cut in FDSOI 28 nm is detailed in chapter 5. Results of the PhD have been disseminated with 4 patent proposals, 2 papers in international conferences, a first paper accepted in an international journal and a second but only submitted paper in an international journal.

L'introduction d'une contrainte mécanique dans le canal de MOSFETs sur SOI est indispensable pour les noeuds technologiques sub-22 nm. Son efficacité dépend de la géométrie et des règles de dessin du dispositif. L'impact des étapes du procédé de fabrication des transistors (gravure des zones actives, formation de la grille métallique, implantation des Source/Drain (S/D)) sur la contrainte du silicium contraint sur isolant (sSOI) a été mesuré par diffraction des rayons X en incidence rasante (GIXRD). Parallèlement, le gain en performances de MOSFETs sur sSOI a été quantifié par rapport au SOI (100% de gain en mobilité pour des nMOS longs et larges (L=W=10 μm), 35% de gain en courant de drain à saturation (IDsat) pour des nMOS courts et étroits (L=25 nm, W=77 nm)). Des structures contraintes innovantes ont aussi été étudiées. Un gain en IDsat de 37% (18%) pour des pMOS sur SOI (sSOI) avec des S/D en SiGe est démontré par rapport au sSOI avec des S/D en Si, pour une longueur de grille de 60 nm et des films de 15 nm d'épaisseur. Des mesures GIXRD, couplées à des simulations mécaniques, ont permis d'étudier et d'optimiser des structures originales avec transfert de contrainte d'une couche enterrée précontrainte (en SiGe ou en nitrure) vers le canal.

Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence. / Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study.

En exploitant la fonction d’amplification intrinsèque fournie par les transistors UTBB FDSOI, nous avons présenté des ISFET ultra sensibles. L'intégration de la fonctionnalité de détection a été réalisée en back end of line (BEOL), ce qui offre les avantages d'une fiabilité et d'une durée de vie accrues du capteur, d'une compatibilité avec le processus CMOS standard et d'une possibilité d'intégration d'un circuit diviseur capacitif. Le fonctionnement des MOSFETs, sans une polarisation appropriée de la grille avant, les rend vulnérables aux effets de grilles flottantes indésirables. Le circuit diviseur capacitif résout ce problème en polarisant la grille avant tout en maintenant la fonctionnalité de détection sur la même grille par un couplage capacitif au métal commun du BEOL. Par conséquent, le potentiel au niveau du métal BEOL est une somme pondérée du potentiel de surface au niveau de la grille de détection et de la polarisation appliquée au niveau de la grille de contrôle. Le capteur proposé est modélisé et simulé à l'aide de TCAD-Sentaurus. Un modèle mathématique complet a été développé. Il fournit la réponse du capteur en fonction du pH de la solution (entrée du capteur) et des paramètres de conception du circuit diviseur capacitif et du transistor UTBB FDSOI. Dans ce cas, des résultats cohérents ont été obtenus des travaux de modélisation et de simulation, avec une sensibilité attendue de 780 mV / pH correspondant à un film de détection ayant une réponse de Nernst. La modélisation et la simulation du capteur proposé ont également été validées par une fabrication et une caractérisation du capteur de pH à grille étendue avec validation de son concept. Ces capteurs ont été développés par un traitement séparé du composant de détection de pH, qui est connecté électriquement au transistor uniquement lors de la caractérisation du capteur. Ceci permet une réalisation plus rapide et plus simple du capteur sans avoir besoin de masques et de motifs par lithographie. Les capteurs à grille étendue ont présenté une sensibilité de 475 mV/pH, ce qui est supérieur aux ISFET de faible puissance de l'état de l’art. Enfin, l’intégration de la fonctionnalité de détection directement dans le BEOL des dispositifs FDSOI UTBB a été poursuivie. Une sensibilité expérimentale de 730 mV/pH a été obtenue, ce qui confirme le modèle mathématique et la réponse simulée. Cette valeur est 12 fois supérieure à la limite de Nernst et supérieure aux capteurs de l'état de l’art. Les capteurs sont également évalués pour la stabilité, la résolution, l'hystérésis et la dérive dans lesquels d'excellentes performances sont démontrées. / Exploiting the intrinsic amplification feature provided by UTBB FDSOI transistors, we demonstrated ultrahigh sensitive ISFETs. Integration of the sensing functionality was made in the BEOL which gives the benefits of increased reliability and life time of the sensor, compatibility with the standard CMOS process, and possibility for embedding a capacitive divider circuit. Operation of the MOSFETs without a proper front gate bias makes them vulnerable for undesired floating body effects. The capacitive divider circuit addresses these issues by biasing the front gate simultaneously with the sensing functionality at the same gate through capacitive coupling to a common BEOL metal. Therefore, the potential at the BEOL metal would be a weighted sum of the surface potential at the sensing gate and the applied bias at the control gate. The proposed sensor is modeled and simulated using TCAD-Sentaurus. A complete mathematical model is developed which provides the output of the sensor as a function of the solution pH (input to the sensor), and the design parameters of the capacitive divider circuit and the UTBB FDSOI transistor. In that case, consistent results have been obtained from the modeling and simulation works, with an expected sensitivity of 780 mV/pH corresponding to a sensing film having Nernst response. The modeling and simulation of the proposed sensor was further validated by a proof of concept extended gate pH sensor fabrication and characterization. These sensors were developed by a separated processing of just the pH sensing component, which is electrically connected to the transistor only during characterization of the sensor. This provides faster and simpler realization of the sensor without the need for masks and patterning by lithography. The extended gate sensors showed 475 mV/pH sensitivity which is superior to state of the art low power ISFETs. Finally, integration of the sensing functionality directly in the BEOL of the UTBB FDSOI devices was pursued. An experimental sensitivity of 730 mV/pH is obtained which is consistent with the mathematical model and the simulated response. This is more than 12-times higher than the Nernst limit, and superior to state of the art sensors. Sensors are also evaluated for stability, resolution, hysteresis, and drift in which excellent performances are demonstrated.

Silicon-on-insulator is a key technology which ensures continuation of Moore’s law. This document investigates the impact of orientation, confinement, and strain on the electronic structure of thin silicon slabs using density functional theory. Moreover a systematic comparison of FDSOI device characteristics using parameters of both the default bulk material and that of the studied slab material is also performed. The comparative study of low index orientations show that confinement not only widens the band gap but also transforms the band gap type. Moreover, it is found that for thin silicon layers, strain can alter band gap and band gap type. By summarizing the findings for different crystal orientations, we demonstrate that the consideration of the electronic structure of strained and confined silicon is of high relevance for modelling actual devices with ultra thin body.

No description available.