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Microarchitectural Level Power Analysis And Optimization In Single Chip Parallel ComputersRamachandran, Priyadarshini 29 July 2004 (has links)
As device technologies migrate into Deep Submicron (DSM) feature sizes, high-performance power-efficient computer architectures that keep pace with improving technologies need to be explored. Technology scaling increases the effects of wire latencies, inductive effects, noise and crosstalk in on-chip communication, limiting the performance of DSM designs. Power efficient performance gains from Instruction Level Parallelism (ILP) are reaching a limit. Single-Chip Parallel Computers are promising solutions to the DSM design challenges and the performance limitations of ILP. These systems are explicitly modular architectures that efficiently support Thread Level Parallelism (TLP) while avoiding global signals and shared resources.
Microarchitectural level power analysis is required for evaluating the feasibility of newly conceived architectures in terms of power dissipation and energy efficiency. Accounting for power in the early stages of design shortens the time-to-market due to reduced design iteration times. Power optimizations at the architectural level can yield large power savings. This thesis proposes a microarchitectural level power estimation and analysis infrastructure for Single Chip Parallel Computers. The power estimation tool and the analysis methodology are developed based on the Single Chip Message-Passing Parallel (SCMP) Computer and can be extended to other Single Chip Parallel Computers. The thesis focuses on the development of power estimation models, construction of the power analysis tool, study of the power advantages of the architecture and identification of subsystems requiring power optimization. / Master of Science
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Implementation of a Hardware-Optimized MPI Library for the SCMP MultiprocessorPoole, Jeffrey Hyatt 16 August 2004 (has links)
As time progresses, computer architects continue to create faster and more complex microprocessors using techniques such as out-of-order execution, branch prediction, dynamic scheduling, and predication. While these techniques enable greater performance, they also increase the complexity and silicon area of the design. This creates larger development and testing times. The shrinking feature sizes associated with newer technology increase wire resistance and signal propagation delays, further complicating large designs. One potential solution is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP makes use of an architecture where a number of simple processors are tiled across a single chip and connected by a fast interconnection network. The system is designed to take advantage of thread-level parallelism and to keep wire traces short in preparation for even smaller integrated circuit feature sizes.
This thesis presents the implementation of the MPI (Message-Passing Interface) communications library on top of SCMP's hardware communication support. Emphasis is placed on the specific needs of this system with regards to MPI. For example, MPI is designed to operate between heterogeneous systems; however, in the SCMP environment such support is unnecessary and wastes resources. The SCMP network is also designed such that messages can be sent with very low latency, but with cooperative multitasking it is difficult to assure a timely response to messages. Finally, the low-level network primitives have no support for send operations that occur before the receiver is prepared and that functionality is necessary for MPI support. / Master of Science
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Design and Analysis of Four Architectures for FPGA-Based Cellular ComputingMorgan, Kenneth J. 09 November 2004 (has links)
The computational abilities of today's parallel supercomputers are often quite impressive, but these machines can be impractical for some researchers due to prohibitive costs and limited availability. These researchers might be better served by a more personal solution such as a "hardware acceleration" peripheral for a PC. FPGAs are the ideal device for the task: their configurability allows a problem to be translated directly into hardware, and their reconfigurability allows the same chip to be reprogrammed for a different problem.
Efficient FPGA computation of parallel problems calls for cellular computing, which uses an array of independent, locally connected processing elements, or cells, that compute a problem in parallel. The architecture of the computing cells determines the performance of the FPGA-based computer in terms of the cell density possible and the speedup over conventional single-processor computation.
This thesis presents the design and performance results of four computing-cell architectures. MULTIPLE performs all operations in one cycle, which takes the least amount of time but requires the most chip area. BIT performs all operations bit-serially, which takes a long time but allows a large cell density. The two other architectures, SINGLE and BOOTH, lie within these two extremes of the area/time spectrum.
The performance results show that MULTIPLE provides the greatest speedup over common calculation software, but its usefulness is limited by its small cell density. Thus, the best architecture for a particular problem depends on the number of computing cells required. The results also show that with further research, next-generation FPGAs can be expected to accelerate single-processor computations as much as 22,000 times. / Master of Science
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Balancing Performance, Area, and Power in an On-Chip NetworkGold, Brian 06 August 2003 (has links)
Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire resistance and delay increase, limiting architects from scaling designs centered around a single thread of execution. Where previous decades have focused on exploiting instruction-level parallelism, emerging applications such as streaming media and on-line transaction processing have shown greater thread-level parallelism. Finally, the increasing gap between processor and off-chip memory speeds has constrained performance of memory-intensive applications.
The Single-Chip Message Passing (SCMP) parallel computer sits at the confluence of these trends. SCMP is a tiled architecture consisting of numerous thread-parallel processor and memory nodes connected through a structured interconnection network. Using an interconnection network removes global, ad-hoc wiring that limits scalability and introduces design complexity. However, routing data through general purpose interconnection networks can come at the cost of dedicated bandwidth, longer latency, increased area, and higher power consumption. Understanding the impact architectural decisions have on cost and performance will aid in the eventual adoption of general purpose interconnects.
This thesis covers the design and analysis of the on-chip network and its integration with the SCMP system. The result of these efforts is a framework for analyzing on-chip interconnection networks that considers network performance, circuit area, and power consumption. / Master of Science
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Monitoring a řízení teplovodních ventilů regulace vytápění jednočipovým mikropočítačem / Monitoring and controlling of the heating water valves by smart board microcomputerMAŠEK, Roman January 2013 (has links)
The Masters thesis describes the control of heating system in family houses where exists requests for supervising and measuring of sources, energy storages and delivery parts of network. Description includes detail for source education support, overviews to development tools and programming language for microcontrollers. Heating system is built for two sources of energy and every source is steered alone. Source codes are designed into PIC? single-chip processors PIC? 18F4520 and PIC? 16F628A developed by Microchip company. These are deployed in unified boards called embedded board chosen for their accessibility from point of view low and high voltage interfaces. Part application of powerful elements control describes principle of operation and their usage in networks. For on-line control of central equipment is preferred usage of powerful components with servo-mechanism and for simpler usage is good to use passive components. Temperature sensor read current value in cross points of network where are media mixed or saved. Processors provides except own control jobs information interface for users too. Used SW is well arranged, faithful and includes routine for source code optimizing. The example of controlled system is actuators in family house heating with high and low temperature circuits which are controlled by industrial systems as current gas coopers.
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Fourier Filter Integration on In-house Fabricated P-N PhotodetectorsLawandi, Roseanna George 30 May 2019 (has links)
No description available.
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Reconfigurable RF and Wireless Architectures Using Ultra-Stable Micro- and Nano-Electromechanical Oscillators: Emerging Devices, Circuits, and SystemsISLAM, MOHAMMAD SAIFUL 01 June 2020 (has links)
No description available.
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Robuster Entwurf und statistische Modellierung für Bildsensoren mit hochparalleler analoger BildverarbeitungseinheitGraupner, Achim 22 April 2013 (has links) (PDF)
Die gemeinsame Integration von Bildsensor und analoger hochparalleler Verarbeitungseinheit stellt eine Möglichkeit zur Realisierung von leistungsfähigen ein-chip Bildaufnahmesystemen dar. Die vorliegende Arbeit liefert Beiträge zum systematischen Entwurf von derartigen Systemen und analysiert bekannte und neuartige Schaltungstechniken bezüglich ihrer Eignung für deren Implementierung. Anhand des vom Autor mitentwickelten CMOS-Bildsensors mit hochparalleler analoger Bildverarbeitungseinheit werden die vorgestellten Methoden und Schaltungstechniken demonstriert.
Die Problematik beim Entwurf hochparalleler analoger Systeme besteht in der im Vergleich zu digitalen Systemen geringen Automatisierbarkeit. Es ist kein top-down-Entwurf möglich, da nicht jede beliebige Funktion mit beliebiger Genauigkeit realisierbar ist. Um die jeweilige Genauigkeit der Funktionsblöcke bei der Analyse des hochparallelen Systems berücksichtigen zu können, sind rechenaufwendige Simulationen nötig. Um diesen Rechenaufwand zu senken, wird vorgeschlagen, für die Simulation des Gesamtsystems einen angepaßten Simulator und für die Analyse der schaltungstechnischen Realisierung der Funktionsblöcke konventionelleWerkzeuge für elektrische Netzwerke zu verwenden. Die beiden Simulationsdomänen werden mit Hilfe von numerischen Verhaltensmodellen verbunden. Durch diese Trennung wird die Simulation des Gesamtsystems als Bestandteil des Entwurfsflusses praktikabel.
Für die Bewertung, inwieweit die zufälligen Schwankungen der Bauelementeparameter das Verhalten von Baublöcken beeinflussen, wird die Varianzanalyse als Alternative zur konventionellen Monte-Carlo-Analyse vorgeschlagen. Die Varianzanalyse ist wesentlich weniger rechenaufwendig und liefert genaue Resultate für alle Schaltungseigenschaften mit hinreichend glatten Parameterabhängigkeiten, wenn die Bauelementeparameter als normalverteilt und statistisch unabhängig angenommen werden können. Sie hat darüberhinaus den Vorteil, das Schaltungsverständnis für den Entwerfer zu erhöhen, da sofort die Bauelementeparameter mit dem größten Einfluß auf das Schaltungsverhalten identifiziert werden können.
Der Vergleich verschiedener Schaltungstechniken hat gezeigt, daß zeitdiskrete wertkontinuierliche Verfahren, bei denen die Information als Strom repräsentiert wird, für die Realisierung von hochparallelen analogen Systemen besonders geeignet sind. Als besonderer Vorteil ist die weitestgehende Unabhängigkeit des Verhaltens derartiger Schaltungen von Bauelementeparametern hervorzuheben.Weitere Schaltungstechniken, deren Verhalten von zufälligen Parameterabweichungen nur wenig beeinflußt werden, sind in einer Taxonomie zusammengefaßt.
Es wurde ein CMOS-Bildsensor mit hochparalleler analoger Bildverarbeitungseinheit und digitaler Ausgabe realisiert. Der current-mode-Bildsensor ist separat von der Verarbeitungseinheit angeordnet. Es wurden vier verschiedene Realisierungsmöglichkeiten untersucht und eine konventionelle integrierende voltage-mode Pixelzelle mit nachfolgendem differentiellen Spannungs- Strom-Wandler realisiert. Das Rechenfeld ist für die räumliche Faltung oder lineare Transformation von Bilddaten mit digital bereitzustellenden Koeffizienten ausgelegt. Dessen Operation basiert auf einer bit-weisen analogen Verarbeitung. Der Schaltkreis wurde erfolgreich getestet. Die nachgewiesene Bildqualität deckt sich in guter Näherung mit den bei der Simulation des Gesamtsystems getroffenen Vorhersagen / The joined implementation of an image sensor and a highly parallel analog processing unit is an advantageous approach for realizing efficient single-chip vision systems. This thesis proposes a design flow for the development of such systems. Moreover known and novel circuit techniques are analysed with respect for their suitability for the implementation of highly parallel systems. The presented methodologies and circuit techniques are demonstrated at the example of a CMOS image sensor with an embedded highly parallel analog image processing unit in whose design the author was involved.
One of the major problems in designing highly parallel analog circuits is the low automation compared to the design of digital circuits. As not every function can be realized with arbitrary accuracy top-down-design is not feasible. So, when analysing the system behaviour the respective precision of each function block has to be considered. As this is a very demanding task in terms of computing power, it is proposed to use a dedicated tool for the simulation of the system and conventional network analysis tools for the inspection of the circuit realizations. Both simulation domains are combined by means of numerical behavioural models. By using separate tools system-simulations of highly parallel analog systems as a part of the design flow become practicable.
Variance analysis basing on parameter sensitivities is proposed as an alternative to the conventional Monte-Carlo-analysis for investigating the influence of random device parameter variations on the system behaviour. Variance analysis requires much less computational effort while providing accurate results for all circuit properties with sufficiently smooth parameter dependencies if the random parameters can be assumed normally distributed and statistically independent. Additionally, variance analysis increases the designer’s knowledge about the circuit, as the device parameters with the highest influence on the circuit performance can immediately be identified.
The comparison of various circuit techniques has shown, that sampled-time continuous-valued current-mode principles are the best choice for realizing highly parallel analog systems. A distinctive advantage of such circuits is their almost independence from device parameters. A selection of further circuit techniques with low sensitivity to random device parameter variations are summarized in a taxonomy.
A CMOS image sensor with embedded highly parallel analog image processing unit has been implemented. The image sensor provides a current-mode output and is arranged separate from the processing unit. Four different possibilities for realizing an image sensor have been analysed. A conventional integrating voltage-mode pixel cell with a succeeding differential voltage- to-current-converter has been selected. The processing unit is designed for performing spatial convolution and linear transformation with externally provided digital kernels. It operates in bit-wise analog manner. The chip has been tested successfully. The measured image quality in good approximation corresponds with the estimations made with system simulations.
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Robuster Entwurf und statistische Modellierung für Bildsensoren mit hochparalleler analoger BildverarbeitungseinheitGraupner, Achim 28 November 2003 (has links)
Die gemeinsame Integration von Bildsensor und analoger hochparalleler Verarbeitungseinheit stellt eine Möglichkeit zur Realisierung von leistungsfähigen ein-chip Bildaufnahmesystemen dar. Die vorliegende Arbeit liefert Beiträge zum systematischen Entwurf von derartigen Systemen und analysiert bekannte und neuartige Schaltungstechniken bezüglich ihrer Eignung für deren Implementierung. Anhand des vom Autor mitentwickelten CMOS-Bildsensors mit hochparalleler analoger Bildverarbeitungseinheit werden die vorgestellten Methoden und Schaltungstechniken demonstriert.
Die Problematik beim Entwurf hochparalleler analoger Systeme besteht in der im Vergleich zu digitalen Systemen geringen Automatisierbarkeit. Es ist kein top-down-Entwurf möglich, da nicht jede beliebige Funktion mit beliebiger Genauigkeit realisierbar ist. Um die jeweilige Genauigkeit der Funktionsblöcke bei der Analyse des hochparallelen Systems berücksichtigen zu können, sind rechenaufwendige Simulationen nötig. Um diesen Rechenaufwand zu senken, wird vorgeschlagen, für die Simulation des Gesamtsystems einen angepaßten Simulator und für die Analyse der schaltungstechnischen Realisierung der Funktionsblöcke konventionelleWerkzeuge für elektrische Netzwerke zu verwenden. Die beiden Simulationsdomänen werden mit Hilfe von numerischen Verhaltensmodellen verbunden. Durch diese Trennung wird die Simulation des Gesamtsystems als Bestandteil des Entwurfsflusses praktikabel.
Für die Bewertung, inwieweit die zufälligen Schwankungen der Bauelementeparameter das Verhalten von Baublöcken beeinflussen, wird die Varianzanalyse als Alternative zur konventionellen Monte-Carlo-Analyse vorgeschlagen. Die Varianzanalyse ist wesentlich weniger rechenaufwendig und liefert genaue Resultate für alle Schaltungseigenschaften mit hinreichend glatten Parameterabhängigkeiten, wenn die Bauelementeparameter als normalverteilt und statistisch unabhängig angenommen werden können. Sie hat darüberhinaus den Vorteil, das Schaltungsverständnis für den Entwerfer zu erhöhen, da sofort die Bauelementeparameter mit dem größten Einfluß auf das Schaltungsverhalten identifiziert werden können.
Der Vergleich verschiedener Schaltungstechniken hat gezeigt, daß zeitdiskrete wertkontinuierliche Verfahren, bei denen die Information als Strom repräsentiert wird, für die Realisierung von hochparallelen analogen Systemen besonders geeignet sind. Als besonderer Vorteil ist die weitestgehende Unabhängigkeit des Verhaltens derartiger Schaltungen von Bauelementeparametern hervorzuheben.Weitere Schaltungstechniken, deren Verhalten von zufälligen Parameterabweichungen nur wenig beeinflußt werden, sind in einer Taxonomie zusammengefaßt.
Es wurde ein CMOS-Bildsensor mit hochparalleler analoger Bildverarbeitungseinheit und digitaler Ausgabe realisiert. Der current-mode-Bildsensor ist separat von der Verarbeitungseinheit angeordnet. Es wurden vier verschiedene Realisierungsmöglichkeiten untersucht und eine konventionelle integrierende voltage-mode Pixelzelle mit nachfolgendem differentiellen Spannungs- Strom-Wandler realisiert. Das Rechenfeld ist für die räumliche Faltung oder lineare Transformation von Bilddaten mit digital bereitzustellenden Koeffizienten ausgelegt. Dessen Operation basiert auf einer bit-weisen analogen Verarbeitung. Der Schaltkreis wurde erfolgreich getestet. Die nachgewiesene Bildqualität deckt sich in guter Näherung mit den bei der Simulation des Gesamtsystems getroffenen Vorhersagen / The joined implementation of an image sensor and a highly parallel analog processing unit is an advantageous approach for realizing efficient single-chip vision systems. This thesis proposes a design flow for the development of such systems. Moreover known and novel circuit techniques are analysed with respect for their suitability for the implementation of highly parallel systems. The presented methodologies and circuit techniques are demonstrated at the example of a CMOS image sensor with an embedded highly parallel analog image processing unit in whose design the author was involved.
One of the major problems in designing highly parallel analog circuits is the low automation compared to the design of digital circuits. As not every function can be realized with arbitrary accuracy top-down-design is not feasible. So, when analysing the system behaviour the respective precision of each function block has to be considered. As this is a very demanding task in terms of computing power, it is proposed to use a dedicated tool for the simulation of the system and conventional network analysis tools for the inspection of the circuit realizations. Both simulation domains are combined by means of numerical behavioural models. By using separate tools system-simulations of highly parallel analog systems as a part of the design flow become practicable.
Variance analysis basing on parameter sensitivities is proposed as an alternative to the conventional Monte-Carlo-analysis for investigating the influence of random device parameter variations on the system behaviour. Variance analysis requires much less computational effort while providing accurate results for all circuit properties with sufficiently smooth parameter dependencies if the random parameters can be assumed normally distributed and statistically independent. Additionally, variance analysis increases the designer’s knowledge about the circuit, as the device parameters with the highest influence on the circuit performance can immediately be identified.
The comparison of various circuit techniques has shown, that sampled-time continuous-valued current-mode principles are the best choice for realizing highly parallel analog systems. A distinctive advantage of such circuits is their almost independence from device parameters. A selection of further circuit techniques with low sensitivity to random device parameter variations are summarized in a taxonomy.
A CMOS image sensor with embedded highly parallel analog image processing unit has been implemented. The image sensor provides a current-mode output and is arranged separate from the processing unit. Four different possibilities for realizing an image sensor have been analysed. A conventional integrating voltage-mode pixel cell with a succeeding differential voltage- to-current-converter has been selected. The processing unit is designed for performing spatial convolution and linear transformation with externally provided digital kernels. It operates in bit-wise analog manner. The chip has been tested successfully. The measured image quality in good approximation corresponds with the estimations made with system simulations.
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