The metallic single electron transistor (SET) has been shown to provide charge sensitivity on the order of 10-6 e/(Hz)1/2, when operated as a charge amplifier. This makes it an ideal candidate for low-noise measurement schemes, such as monitoring nano-mechanical oscillations, or reading out the charge state of a quantum bit. The SET operates by exploiting quantum tunneling across an ‘island’ between two insulating tunnel junctions, and can be modulated by a capacitively coupled gate electrode. A metallic SET has been fabricated and characterized at low frequencies. The device was fabricated on a silicon substrate coated with a bi-layer resist, using electron beam lithography. The Al-AlOx¬-Al tunnel junctions were created using double angle evaporation. Samples were tested near 300 mK in a custom helium-3 cryostat system. Results which characterize the SET parameters and conductance behaviour were obtained, in both the superconducting and normal states. This thesis contains a discussion of the fabrication procedures and dc measurement techniques required to produce and test a single electron transistor. Relevant background theory relating to SET operation and cryogenic laboratory techniques is presented. A brief discussion of proposed future experiments using a dual gate radio frequency SET as a more sensitive amplifier is introduced. / Thesis (Master, Physics, Engineering Physics and Astronomy) -- Queen's University, 2007-08-01 14:07:55.427

No description available.

Universiẗat, Diss., 1990--Heidelberg.

CMOS Technology has advanced for decades under the rule of Moore's law. But all good things must come to an end. Researchers estimate that CMOS will reach a lower limit on feature size within the next 10 to 15 years. In order to assure further progress in the field, new computing architectures must be investigated. These nanoscale architectures are many and varied. It remains to be seen if any will become a legitimate successor to CMOS. Single electron tunneling is a process by which electrons can be trans- ported (tunnel) across a thin insulating surface. A conducting island sepa rated by a pair of quantum tunnel junctions creates a Single Electron Transistor (SET). SETs exhibit higher functionality than traditional MOSFETs, and function best at very small feature sizes, in the neighborhood of 1nm. Many circuits must be developed before SETs can be considered a viable contender to CMOS technology. One important circuit is the Digital to Analog Converter (DAC). DACs are present on many microprocessors and microcontrollers in use today and are necessary in many situations. While other SET circuits have been proposed, including ADCs, no DAC design exists in open literature. We propose three possible SET DAC designs and characterize them with an HSPICE SET simulation model. The first design is a charge scaling architecture similar to what is frequently used in CMOS. The second two designs are based on a current steering architecture, but are unique in their implementation with SETs. / Master of Science

Le transistor monoélectronique, SET ou single-electron transistor, a été considéré comme étant l’une des alternatives au CMOS lorsqu’il atteindra le « mur technologique ». Le SET se caractérise comme un dispositif ultra faible puissance et nanométrique, mais son faible gain et sa grande dépendance à la température ont fait en sorte que la technologie SET a perdu du momentum vis-à-vis la communauté scientifique. Cependant, en ne considérant pas la technologie SET comme une remplaçante du MOSFET, mais comme quelque chose qui permettrait d’ajouter des fonctionnalités aux circuits CMOS, elle semble être très prometteuse. Cette niche est habituellement appelée l’hybridation SET-CMOS. Ce mémoire débute par une validation des circuits hybrides SET-CMOS présents dans la littérature en remplaçant le modèle de simulation de SET par un modèle beaucoup plus réaliste. De ces circuits hybrides, aucun ne fonctionnera étant donné les courants de fuite trop importants. Le re-design de ces circuits avec ces architectures a été fait avec le bon modèle SET et une technologie CMOS 22 nm, mais leurs performances n’ont pas suffi pour démontrer leur bon fonctionnement (Plage de tension de sortie très faible, aucune bande passante, circuits incomplets, forte dépendance du circuit à ce qui est connecté à la sortie, etc.). Cela a amené à la création de deux nouvelles architectures de circuits de lecture hybrides SET-CMOS. Chaque circuit est conçu avec une technologie CMOS 22 nm. L’une des architectures est principalement adaptée à une application de dispositif capteur SET, où le SET serait éloigné d’un circuit CMOS. Dans l’exemple démontré, le circuit avec le capteur SET donne une sensibilité de 8.4 V par électron peu importe la charge connectée à la sortie du circuit. La nouvelle architecture inventée servirait d’étage tampon entre un circuit numérique fait de SET et un circuit numérique CMOS conventionnel. Dans la littérature, les circuits numériques SET n’ont pas de charge typique lors de leur simulation (ex : un inverseur CMOS), ce qui fausse les résultats en promettant une fréquence haute d’opération impossible à atteindre lors d’une utilisation typique. Ce circuit de lecture numérique fait la lecture du circuit numérique SET, fait le passage entre les deux alimentations différentes et est en mesure de supporter un inverseur CMOS conventionnel à 440 MHz. La consommation de ce circuit n’est que de 5.3 nW lors d’une utilisation à 200 MHz. Cette faible consommation est tout à fait en phase avec l’utilisation de circuits numériques SET qui consomment très peu. Chaque nouvelle architecture inventée a été simulée avec l’ensemble des effets parasites que les interconnexions apportent aux circuits. Les simulations procurent ainsi des résultats plus réalistes. Un procédé de fabrication de circuits hybrides SET-CMOS, où les dispositifs SET sont fabriqués sur le BEOL des puces CMOS avancées, a été développé et testé. Il intègre le procédé nanodamascène, pour la fabrication des nanodispositifs, et la fabrication d’interconnexions/vias afin de relier le CMOS avec les SET. Une démarche pour la validation des dispositifs CMOS a aussi dû être développée et testée. Afin de s’adapter aux dispositifs CMOS à notre disposition, une conception de circuit hybride SET-CMOS a été faite. La fabrication d’un premier prototype recréant un circuit hybride SET-CMOS fût réalisée.

Current-controlled logic and single electron logic processors have been investigated with respect to thermal-induced bit error. A maximal error rate for both logic processors is regarded as one bit-error/year/chip. A maximal clock frequency and an information channel capacity at a given operation current are derived when a current-controlled logic processor works without error. An available operation range in a current-controlled processor with 100 million elements is discussed. The dependence of an error-free condition on temperature in single electron logic processors is derived. The size of the quantum dot of single electron transistor is predicted when a single electron logic processor with the a billion single electron transistors works without error at room temperature.

In this thesis, I will present the experimental results of the dynamics of superconducting single electron transistors (sSETs), under the influence of tunable dissipation. The sSET, consisting of two dc SQUIDs in series and the third gate electrode, is deposited onto a GaAs/AlGaAs heterostructure which contains a two dimensional electron gas plane 100nm beneath the substrate surface. The Josephson coupling energy, charging energy and dissipation related Hamiltonian can all be tuned in situ, while keeping others unchanged. We measured the switching current statistics and the transport properties, as a function of the dissipation and gate charge at different temperatures. If the sSET is in the classical regime where phase is a good quantum variable, we found that the switching current and corresponding Josephson energy decrease as dissipation increases. Our observation agrees qualitatively with the theoretical calculation of a single Josephson junction with dominant Josephson energy, in a frequency dependent dissipative environment where energy barrier decreases as dissipation increases in thermally activated escape regime. This dissipation dependence result can be understood as the consequence of a reduced quantum fluctuations in the charge numbers. Whereas in the charging regime, the switching current shows a 1e periodicity with respect to gate charge, indicating a pronounced charging effect. At a specific gate charge number, quantum fluctuations of the phase variable are compressed as dissipation increases, resulting in an enhanced switching current and Josephson energy. This result matches the theory of a sSET capacitively coupled to a dissipative environment qualitatively. The temperature dependence of the switching current histogram indicates the existence of both quantum and classical thermal phase diffusion. Moreover, quantum charge fluctuations are minimized at the degeneracy point, causing a sharp dip on the width of the switching current histogram. For a sSET with comparable Josephson energy and charging energy, quantum fluctuations of both phase and charge variables are significant. The influence of dissipation on the dynamics of the device is distinct in the classical and charging regimes. Dissipation compresses quantum phase fluctuations in the charging regime, whereas reduces the quantum charge fluctuations in the classical regime. The transition between these two regimes is found to be determined by the tunnel resistance of the SQUID. The competition between Josephson and charging energies, however, is not the intrinsic parameter of this transition. Our results imply that a detailed theoretical calculation of a sSET with comparable Josephson coupling energy and charging energy under the influence of dissipation is needed.

Current-controlled logic and single electron logic processors have been investigated with respect to thermal-induced bit error. A maximal error rate for both logic processors is regarded as one bit-error/year/chip. A maximal clock frequency and an information channel capacity at a given operation current are derived when a current-controlled logic processor works without error. An available operation range in a current-controlled processor with 100 million elements is discussed. The dependence of an error-free condition on temperature in single electron logic processors is derived. The size of the quantum dot of single electron transistor is predicted when a single electron logic processor with the a billion single electron transistors works without error at room temperature.

In the past decade, nanomechanical resonators have found use in the work towards understanding mesoscopic quantum systems and the necessary validation of quantum mechanics on this scale. In 2010, the observation and state manipulation of a nanomechanical quantum system was achieved for the first time by O'Connell et al.. In 2002, Knobel and Cleland proposed to use a radio frequency superconducting single-electron transistor (RF-SSET), a fast and sensitive charge amplifier, to sense the quantum-limited motion of a piezoelectrically coupled nanomechanical resonator. The work presented in this thesis is towards the realization of the RF-SSET component of this device. An in-house fabrication recipe for making SETs with tunnel junction areas < 100^2 nm^2 and resistances between 20 kΩ and 150 kΩ was developed, in the end producing six SETs with resistances (36 ± 8) kΩ that were not susceptible to aging effects. Three measurement circuits were designed and used to characterize one of these SETs in the superconducting state (SSET) and operated in the DC and RF modes in a cryostat at a base temperature of 320~mK. Lock-in measurements revealed the SSET junction capacitances as 206 and 305 aF, contributing to a charging energy of (296 ± 11) x 10^(-6) eV. The resonant LC tank, which permitted RF operation, was also characterized at base temperature. The charge sensitivity of the RF-SSET was 6.8 x 10^(-5) e/√Hz (with uncertainty between 9.6 x 10^(-4) e/√Hz and 3.5 x 10^(-5) e/√Hz). With moderate improvements to the impedance matching network formed with the LC tank and greater junction resistances, an RF-SSET charge sensitivity on the order of 10^(-6) e/√Hz, required for sensing the quantum-limited motion of the nanomechanical resonator, should be achieved. / Thesis (Master, Physics, Engineering Physics and Astronomy) -- Queen's University, 2010-08-10 17:38:43.798

As a result of increasing demand of power in the modern society, energy storage/consumption is playing a more important role on future economics. Therefore energy storage systems which are more environmentally friendly, low-cost and high-performance have attracted much attention. Among electrochemical systems, supercapacitors are considered as a prominent candidate for the modern energy storage systems due to the high power density, high charge/discharge rate, and long lifetimes. Nevertheless, the performance of supercapacitors is limited by the significant disadvantage of low energy density. Metal oxides with high pseudocapacitance such as MnO2 are used as the electrode materials for supercapacitors to resolve the lack of energy density in supercapacitors. The specific capacitance is notably enhanced by the metal oxides because of the reversible redox reactions. Previous studies confirmed that only a thin layer of MnO2 is involved in the redox process and is electrochemically active, which makes surface area a critical factor of energy storage. To increase surface area of MnO2, ZnO nanostructure is introduced in the electrode material as a template for electrodeposition of MnO2. In the first part of the research, we synthesize a nanomaterial which combines 0-1-2 dimensional properties of different nanostructures and significantly increases the energy capacity of MnO2. iv In the second part of the research, we demonstrate an in situ synthesis of a hybrid device that combines two materials to investigate the individual characteristic of two nanomaterials. In this study, a ZnO nanorod interface on Au nanoparticle arrays is fabricated, and results in the photo-modulation of the array characteristics. We find the use of nanoparticle arrays as electrochemical systems by electrodepositing ZnO on Au nanoparticle arrays. The method expands their potential use in sensors, multifunctional materials, single electron transistors and nanoscale energy systems. Characteristic behavior of Au nanoparticle arrays including Coulomb blockade at room temperature, single electron charging effects and a power law dependence in current-voltage were observed, and Schottky behavior and photocurrent generation due to the ZnO nanorods were also proved. From the modulation of the threshold voltage of the Au array due to the electron-hole pairs generated by photo excitation in the ZnO rods, it can be seen that the system also has coupling between the Au nanoparticles and ZnO rods other than the individual characteristics. Au nanoparticles can be used as electrochemical systems with both structural and spatial confinement of the synthesized material. The possibility of using Au nanoparticle chains as electroactive sites significantly expands their potential use in sensors, multifunctional materials, single electron transistors and nanoscale energy systems.