In this work, the design of a CMOS broadband low noise amplifier with inherent high performance single-to-differential conversion is presented. These characteristics are driven by the double quadrature single conversion digital television tuner which requires accurately balanced differential signals to perform its function and to improve image rejection. A three-stage amplifier is designed to satisfy several requirements of front-end circuits at the same time. The resistive shunt-feedback topology is adopted to implement a single-ended broadband low-noise amplifier as the first stage. The second stage is an on-chip single-to-differential converter, which employs a novel method to improve its balancing performance. A fully differential buffer capable of driving heavy loads is used as the third stage to further suppress the phase and magnitude errors of output differential signals. Fabricated in 0.35??m TSMC standard CMOS technology, the designed broadband front-end amplifier manages to limit the phase error to within ??1.5?? and magnitude error ??0.75dB over 50~850 MHz frequency range, with 16dB gain and a noise figure of 4dB.

In wireless transceiver circuits some of the most prevalent required off-chip components are discrete filters. These components are generally implemented with surface acoustic wave (SAW) or ceramic components. These devices are used in the receiver section for discrimination of incoming radio frequency (RF) signals as well as downconverted intermediate frequency (IF) signals. Presently, with the growing demand for multi-functional wireless consumer devices, the need for full integration of RF and logic circuits in wireless communications systems is becoming increasingly evident. If integrated RF filters with acceptable electrical characteristics could be realized, this might reduce or eliminate the currently required off-chip filters, prospectively decreasing the complexity, size, and cost of future wireless transceiver circuits and systems. The objective of the present research effort is to implement an integrated Q-enhanced LC bandpass filter in a prospective receiver front-end RF amplifier using the passive and active components available in a standard digital complementary metal-oxide semiconductor (CMOS) process. CMOS is the standard design medium for digital circuitry, and with the increased unity gain or transit frequency (fT) values that accompany steadily shrinking CMOS device sizes, the implementation of gigahertz frequency communications circuits in this medium is increasingly feasible. The circuit design specifically investigated in this work introduces a loss-compensated second-order gigahertz range bandpass filter implemented in a 0.18 쭠digital CMOS process provided by National Semiconductor. This filter incorporates a unique design technique that provides improvements in filter linearity through an independently variable bias level shifting method, while also facilitating prospective single-to-differential signal conversion. One distinctive characteristic of the investigated circuit, in comparison to other RF integrated filter work, is the implementation of a novel integrated transformer feedback method that facilitates magnetically coupled loss-restoration and subsequent filter Q-enhancement. Additionally, this loss restoration method is achieved using a single transistor, in contrast to the multi-transistor cross-coupled transconductor Q-enhancement technique commonly implemented in other previous and current integrated RF filter research.