This research investigates the effect of pedestrian countdown signals (PCS devices) on crossing walking speed of pedestrians at urban signalized intersections. The research considers two age groups: (1) younger pedestrians (ages 20 to 64); and (2) older pedestrians (ages 65 and older). Two pedestrian walking speeds were used for this research: (1) crossing walking speed (speed pedestrians walk crossing a signalized intersection); and (2) normal walking speed (speed pedestrians walk a segment of sidewalk). The research found that PCS devices have an effect on a pedestrians’ crossing walking speed, regardless of age, by decreasing the speed. Older pedestrians alter their walking speed after the installation of PCS devices more than younger pedestrians. Furthermore, after the installation of PCS devices the walking speed of pedestrians shifts from a faster crossing walking speed towards a slower normal walking speed.

This thesis considers the effects of Picture Archive and Communications Systems (PACS), on both patient radiation doses and patient management. PACS is a relatively new technology which acquires, transmits, and stores radiological images digitally. This thesis investigates the doses which are required to produce radiographic images which are acceptable to radiologists and referring clinicians, and compares these doses with those required for the film/screen systems which they are replacing. A review of the literature shows that despite claims of dose reductions, very little good evidence exists about dose changes with the introduction of PACS. A comparison of images of test objects indicates that the images are comparable under limited conditions, that PACS has a much wider latitude than film (>250 mAs), and that contrast detail improves with increase in exposure. Two original observational studies are described in which PACS and film doses are compared for examinations of two groups of adult patients. The results indicate that the doses for PACS equate to those used with a 300 speed film/screen system thus necessitating dose increases of around 30% for the majority of adult patients in the UK. The issue of whether the number of images which are repeated, with additional patient doses, due to unsatisfactory images (rejected images), or unavailability of the images when clinically required (lost images), is addressed and indicates that PACS may allow a dose saving of 1.1 % and 1.4% respectively. The overall result of these studies indicates that the widespread introduction of PACS is likely to increase population doses. Two original studies which consider patients within the Accident and Emergency department are described. These studies aim to produce evidence to justify the introduction of the new technology, despite higher radiation doses, by identifying improvements in patient management which might improve patient outcomes. The results of these studies provide little evidence of such benefits to patients. This thesis concludes that the use of current PAC systems produces an increase in the radiation dose to the adult population in the UK, without demonstrable improvements in patient management.

The tremendous advancement in VLSI technologies in the past decade has fueled the need for intricate tradeoffs among speed, power dissipation and area. With gigahertz range microprocessors becoming commonplace, it is a typical design requirement to push the speed to its extreme while minimizing power dissipation and die area. Multipliers are critical components of many computational intensive circuits such as real time signal processing and arithmetic systems. The increasing demand in speed for floating-point co-processors, graphic processing units, CDMA systems and DSP chips has shaped the need for high-speed multipliers. The focus of our research for modern digital systems is two fold. The first one is to analyze a relatively unexplored logic style called MOS Current Mode Logic (MCML), which is a promising logic technique for the design of high performance arithmetic circuits with minimal power dissipation. The second one is to design high-speed arithmetic circuits, in particular, gigahertz-range multipliers that exploit the many attractive features of the MCML logic style. A small library of MCML gates that form the core components of the multiplier were designed and optimized for high-speed operation. The three 8-bit MCML multiplier architectures designed and simulated in TSMC 0.18 mm CMOS technology are: 3-2-tree architecture with ripple carry adder (Architecture I), 4-2-tree design with ripple carry adder (Architecture II) and 4-2-tree architecture with carry look-ahead adders (Architecture III). Architecture I operates with a maximum throughput of 4.76 GHz (4.76 Billion multiplications per second) and a latency of 3.78 ns. Architecture II has a maximum throughput of 3.3 GHz and a latency of 3 ns and Architecture III has a maximum throughput of 2 GHz and a latency of 3 ns. Architecture I achieves the highest throughput among the three multipliers, but it incurs the largest area and latency, in terms of clock cycle count as well as absolute delay. Although it is difficult to compare the speed of our multipliers with existing ones, due to the use of different technologies and different optimization goals, we believe our multipliers are among the fastest found in contemporary literature. / Master of Science

The research presented in this thesis attempts to investigate the impact of detector failure frequency and failure duration on the accuracy of loop detector speed, flow, and density measurements using a Monte Carlo simulation approach. The inputs to the model are the frequency of failures and failure duration. Several regression models were developed to relate loop detector accuracy to detector failure data. The results showed that the models were consistent and similar for the same location with an R square that ranged between 86% and 94% for all models and in comparing two locations, the differences between the regression models were minor except for the flow model errors, the location had the same trend but the magnitude of the flow RMSE increased by 7.5 to 15%. The second part of the research effort attempts to quantify the impact of inclement weather (precipitation and visibility) on traffic stream free-flow speeds along freeway sections. The analysis is conducted using weather (precipitation and visibility) and loop detector data (speed) obtained from Baltimore, Minneapolis/St. Paul, and Seattle, US. The results demonstrate that visibility alone has a minimum impact on free-flow speed with reductions in the range of 1 to 3%. These reductions only appear as the visibility level falls below 1.2 km. The study demonstrates that the impact of snow is more significant than that of rain for similar intensity levels. Reductions caused by rain are in the neighborhood of 2 to 5% depending on the precipitation intensity while reductions caused by snow are in the neighborhood of 6 to 20%. With regards to freezing rain, higher reductions in free-flow speed were observed when compared to rain and snow. Specifically, the free-flow speed was reduced by 14% at the onset of freezing rain precipitation with a maximum decrease of 27% at freezing rain intensity of about 0.53 cm/h for Baltimore and as the case of Seattle the reduction was found to be constant with 31%. Finally, the paper derives free-flow speed reduction factors that vary as a function of the precipitation type and intensity level. These reduction factors can be incorporated within the Highway Capacity Manual's procedures. / Master of Science

The thesis describes a novel 4-quadrant DC-DC converter, supplied by a 28V DC voltage source, with an output voltage which may be continuously varied between +180V and -180V DC. A prototype 1.2kW DC-DC converter was designed and built, with emphasis given to the optimization of both the converter size and efficiency. This was achieved by means of a computer-based simulation study, which determined the optimal switching frequency and the size of the inductors and capacitors while maintaining a high unit efficiency. Mos-Gated Bimos switches, which feature the advantages of both mosfets and bipolar transistors, were developed to achieve high switching speed during high power operation. A digital-controlled DC servo system based on a 16-bit Intel 8086 microprocessor was designed, to provide both motor speed and position control. Speed and position detection circuits and the structure and the interfacing arrangement of the microprocessor system were designed and constructed. Several control algorithms were developed, including PID Control Algorithm and Current-Limit Control Algorithm. Based on open loop transfer function of the system, derived through mathematical modelling using the State-Space Averaging Method, the constants for the control algorithms were obtained to meet the dynamic performance specified for the system. Computer simulation was carried out to assist with the design of the converter and the control system. It is expected that drives into which the novel converter is incorporated will find many applications in situations where accurate positional control is required, particularly in battery-operated DC-servo system, such as satellite system, robots and some military vehicles.

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / SAIC, under contract with the Air Force Wright Laboratory, has developed and demonstrated a prototype High Speed Avionics Data Instrumentation System (HADIS). The HADIS system is designed to operate in both the laboratory and in an airborne environment. This paper briefly describes the features of the system including its ability to collect and record data at up to 13.25 MBytes per second, its ability to provide real-time processing of the data, and its ability to rapidly reconfigure its interfaces based on field programmable gate arrays. The paper discusses the need for multiple data paths within the system to allow parallel operations to take place, the need for dedicated access to the recorder subsystem, and methods for allowing selective recording based on the information content of the data. The effort was sponsored by the Test Facility Working Group to provide a common data collection system for Air Force logistics and test and evaluation facilities. The design is owned by the government and may be cost-effectively used by any government agency.

The frequency of a Pulse Width Modulated (PWM) power source can be adjusted to control the speed of an AC machine. Machine response in this mode of operation depends strongly on the quality of the chosen PWM switching strategy. Several methods of PWM waveform synthesis are presented and new methods are introduced. A novel Relaxed Spectrum (RS) algorithm based on a Fourier series expansion of the PWM signal is presented. The algorithm computes sinusoidal and non-sinusoidal switching patterns from a specified set of harmonic coefficients. The RS method is suitable for both full- and half-bridge PWM invertors. Unwanted harmonics inherent in a PWM signal, are exploited to induce excitation into the rotor of a synchronous machine. Rotor mounted diodes are used to rectify the induced currents. 'Rvo novel induced excitation methods are presented which permit accurate control of excitation levels. Whilst the first method uses a single Excitation Harmonic Voltage (EHV) for rotor excitation, an EHV pair is used in the second method to obtain improved machine response. The RS algorithm is applied to obtain a PWM waveform which approximates closest to a given specification. PWM switching patterns are obtained for most possible excitation conditions. Voltage Control Limit Functions (VCLF) are computed which define control limits for several excitation schemes. The response of a computer simulated machine model to an Ideal Test Voltage (lTV) is investigated to assess the performance of the new methods of machine excitation. Simulation reveals that the use of an EHV pair minimises motor torque pulsation. Optimum excitation ratios are then defined in terms of the harmonic indices of a given EHV pair. These ratios are shown to be largely independent of machine parameters. The RS method is used t(] compute generalised sets of PWM switching sequences which can subsequently be applied to a wide range of differently rated machines. Analogue Symmetrical Sample (SS) PWM waveform synthesis methods for induce( excitation are compared with their digital equivalents. It is shown that digital P~ techniques compare favourably and can provide higher excitation levels when a largl fundamental drive voltage is required.

No description available.

No description available.

No description available.