Presented in this work is a novel design technique for a low-phase-noise high-frequency CMOS voltage-controlled oscillator. Phase noise is generated from electrical noise near DC, the oscillation frequency, and its harmonics. In CMOS technology, low-frequency flicker noise dominates the close-in phase noise of the VCO. The proposed technique minimizes the VCO phase noise by seeking to eliminate the effect of flicker noise on the phase noise. This is accomplished by canceling out the DC component of the impulse sensitivity function (ISF) corresponding to each flicker-noise source, thus preventing the up-conversion of low-frequency noise into phase noise. The proposed circuit topology is a modified version of the complementary cross-coupled transconductance VCO, where additional feedback paths are introduced such that a designer can choose the feedback ratios, transistor sizes, and bias voltages to achieve the previously mentioned design objectives. A step-by-step design algorithm is presented along with a MATLAB script to aid in the computation of the ISFs and the phase noise of the VCO. Using this algorithm, a 5-GHz VCO was designed and fabricated in a 0.18μm CMOS process, and then tested for comparison with simulated results.

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<p> This thesis contributes to the computer-aided design (CAD) of spiral inductors and LC resonators with spiral inductors exploiting full-wave electromagnetic (EM) analysis.</p> <p> The spiral inductor is widely used in radio frequency integrated circuits (RF ICs), such as low noise amplifiers (LNA) and voltage controlled oscillators (VCO). The design of spiral inductors has a direct influence on the performance of these circuits. Recently proposed optimization methods for spiral inductors are usually based on circuit models, which are computationally efficient but inaccurate compared with full-wave electromagnetic (EM) simulations.</p> <p> For the first time, we develop an optimization technique for the design of spiral inductors and LC resonators exploiting both the computational efficiency of a (cheap) circuit model and the accuracy of a full-wave EM analysis, based on geometric programming (GP) and space mapping (SM). With the new technique, we can efficiently obtain EM-validated designs with considerable improvement over those obtained with traditional optimization methods.</p> / Thesis / Master of Applied Science (MASc)

<p>This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.</p><p>As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.</p><p>Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.</p><p>Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.</p>

This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors. As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC. Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed. Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

Phase Shifters are one of the most important building cells of the applications in microwave and millimeter-wave range, especially for communications and radar applications / to steer the main beam for electronic scanning. This thesis includes all of the stages starting from the theoretical design stage to the measurements of the phase shifters. In detail, all-pass network phase shifter configuration is used to achieve broadband and ultra wide-band differential phase characteristics. For these reasons, 1 to 2 GHz, 2 to 4 GHz, and 3 to 6 GHz 4-bit, 22.5&deg / phase resolution phase shifter realization with surface micromachined lumped components are designed, simulated, fabricated and measured. Basic building blocks of the phase shifters, i.e., surface micromachined lumped components, square planar spiral inductors and Metal-Insulator-Metal capacitors are designed with EM simulation and lumped equivalent model extractions. The validation of the designed square planar spiral inductors is done with fabrication and measurement steps, very low error, below 1%, between the designs and fabricated samples are observed. Using this knowledge on lumped elements finally phase shifters are designed with surface micromachined lumped components, fabricated using an in house technology provided by METU-MEMS facilities, RF MEMS group. Low phase rms error, good return and insertion loss considerations are aimed, and achieved. In addition to the main work of this thesis, a generalized theoretical calculation method for 2n-1 number of stages all-pass network phase shifters is presented for the first time in literature. A different, new, broadband, and combined phase shifter topology using two-stage all-pass filters is presented. Moreover, the implementation of this idea is proved to be practical to 3 to 6 GHz 5.625&deg / and 11.25&deg / combined phase shifter. A new approach for stage numbers other than power of 2 is indicated, which is different from what is already presented in the literature. An example practical implementation results are provided for the three-stage 4-bit 1 to 6 GHz phase shifter. Also, a small improvement in SRF of the high inductance valued inductors is achieved with the mitering of the corners of square planar spiral inductors. Comparison of the measured data between the normal inductors and mitered versions shows that the first SRF of the inductors are increased about 80 MHz, and second SRF of the inductors are increased about 200 MHz.