In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

Electrostatic Discharges (ESD) is a significant hazard to electronic components and systems. Based on a specific process technology, a given circuit application requires a customized ESD consideration that meets all the requirements such as the core circuit's operating condition, maximum accepted leakage current, breakdown conditions for the process and overall device sizes. In every several years, there will be a new process technology becomes mature, and most of those new technology requires custom design of effective ESD protection solution. And usually the design window will shrinks due to the evolving of the technology becomes smaller and smaller. The ESD related failure is a major IC reliability concern and results in a loss of millions dollars each year in the semiconductor industry. To emulate the real word stress condition, several ESD stress models and test methods have been developed. The basic ESD models are Human Body model (HBM), Machine Mode (MM), and Charge Device Model (CDM). For the system-level ESD robustness, it is defined by different standards and specifications than component-level ESD requirements. International Electrotechnical Commission (IEC) 61000-4-2 has been used for the product and the Human Metal Model (HMM) has been used for the system at the wafer level. Increasingly stringent design specifications are forcing original equipment manufacturers (OEMs) to minimize the number of off-chip components. This is the case in emerging multifunction mobile, industrial, automotive and healthcare applications. It requires a high level of ESD robustness and the integrated circuit (IC) level, while finding ways to streamline the ESD characterization during early development cycle. To enable predicting the ESD performance of IC's pins that are directly exposed to a system-level stress condition, a new the human metal model (HMM) test model has been introduced. In this work, a new testing methodology for product-level HMM characterization is introduced. This testing framework allows for consistently identifying ESD-induced failures in a product, substantially simplifying the testing process, and significantly reducing the product evaluation time during development cycle. It helps eliminates the potential inaccuracy provided by the conventional characterization methodology. For verification purposes, this method has been applied to detect the failures of two different products. Addition to the exploration of new characterization methodology that provides better accuracy, we also have looked into the protection devices itself. ICs for emerging high performance precision data acquisition and transceivers in industrial, automotive and wireless infrastructure applications require effective and ESD protection solutions. These circuits, with relatively high operating voltages at the Input/Output (I/O) pins, are increasingly being designed in low voltage Complementary Metal-Oxide-Semiconductor (CMOS) technologies to meet the requirements of low cost and large scale integration. A new dual-polarity SCR optimized for high bidirectional blocking voltages, high trigger current and low capacitance is realized in a sub 3-V, 180-nm CMOS process. This ESD device is designed for a specific application where the operating voltage at the I/O is larger than that of the core circuit. For instance, protecting high voltage swing I/Os in CMOS data acquisition system (DAS) applications. In this reference application, an array of thin film resistors voltage divider is directly connected to the interface pin, reducing the maximum voltage that is obtained at the core device input down to ± 1-5 V. Its ESD characteristics, including the trigger voltage and failure current, are compared against those of a typical CMOS-based SCR. Then, we have looked into the ESD protection designs into more advanced technology, the 28-nm CMOS. An ESD protection design builds on the multiple discharge-paths ESD cell concept and focuses the attention on the detailed design, optimization and realization of the in-situ ESD protection cell for IO pins with variable operation voltages. By introducing different device configurations fabricated in a 28-nm CMOS process, a greater flexibility in the design options and design trade-offs can be obtained in the proposed topology, thus achieving a higher integration and smaller cell size definition for multi-voltage compatibility interface ESD protection applications. This device is optimized for low capacitance and synthesized with the circuit IO components for in-situ ESD protection in communication interface applications developed in a 28-nm, high-k, and metal-gate CMOS technology. ESD devices have been used in different types of applications and also at different environment conditions, such as high temperature. At the last section of this research work, we have performed an investigation of several different ESD devices' performance under various temperature conditions. And it has been shown that the variations of the device structure can results different ESD performance, and some devices can be used at the high temperature and some cannot. And this investigation also brings up a potential threat to the current ESD protection devices that they might be very vulnerable to the latch-up issue at the higher temperature range.

Tout composant envoyé dans l'espace est soumis à de nombreuses contraintes (radiations, température) qui peuvent conduire à une défaillance de l'ensemble du système. Dans un avenir proche, ces contraintes deviendront de plus en plus critiques à mesure que les agences spatiales développeront des missions visant d'autres planètes, telles que Jupiter, pour lesquelles la contrainte radiative est extrême. Dans ce travail, deux types d'effets dus aux radiations sont étudiés : les effets cumulatifs et les effets transitoires. L'un correspond à la dégradation induite par les radiations au cours du temps, tandis que l'autre correspond à un événement ponctuel qui peut se produire à tout moment lorsque le système est dans l'espace. Pour garantir le bon fonctionnement en vol, des normes de qualification des composants électroniques ont été élaborées par différentes agences spatiales. Toutes ces normes précisent que les effets cumulatifs et transitoires doivent être vérifiés à l'aide de composants intacts pour chaque essai. Par conséquent, les effets cumulatifs sont traités séparément des effets transitoires, alors qu'il y a une forte probabilité qu'ils apparaissent simultanément pendant une mission spatiale. L'étude des effets de synergie est alors le thème principal de cette thèse.Sur un amplificateur opérationnel bipolaire, la réponse de sortie du composant due à un événement transitoire est directement liée aux paramètres internes du composant, qui varient sous l’effet des radiations. A l’aide d’une comparaison entre trois amplificateurs opérationnels différents partageant la même référence, l'impact du design sur la dégradation due aux radiation est étudié.Récemment, des défaillances imprévues ont été reportées pour lesquelles le mode de défaillance semblait indiquer qu'une structure de protection contre les décharges électrostatiques (ESD) était en cause. Par conséquent, pour comprendre si ces protections peuvent causer des défaillances inattendues, la dégradation des « Gate Grounded n-MOSFET » (GGnMOS) est également étudiée. / Any system sent to space is submitted to many constraints (radiations, temperature) which may lead to a failure of the whole system. In a close future, these constraints will become more and more critical as the space agencies are developing missions aiming at others planets such as Jupiter for which the radiative constraint is extremely harsh. In this work, two types of radiation effects are studied: the cumulative effects and the transient effects. One corresponds to the radiation-induced degradation over time, while the other corresponds to a punctual event that can happen at any time when the system is in space. To ensure a proper functioning of a system sent to space, qualifications standards for electronic components have been developed by different space agencies. All of these standards specify that the components must be tested for cumulative and transient effects, using pristine components for each test. Therefore, cumulative effects are treated separately from transient effects, while there is a significant probability that they will appear simultaneously during a space mission. The study of the synergistic effects is then the main frame of this thesis.On a bipolar operational amplifier, the output response of the component due to a transient event is directly related to the internal parameters of the component, which vary over time once in space. Through a comparison between three different operational amplifier sharing the same reference, the impact of the design over the degradation is explained.Lately, some unexpected failures were reported for which the failure mode seemed to indicate that an Electrostatic Discharge (ESD) protection structure was involved. Therefore, to understand if those protections may cause some unexpected failures, the degradation of gate grounded n-MOSFET (GGnMOS) will be investigated next.

<p>This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors.</p><p>As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC.</p><p>Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed.</p><p>Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.</p>

This thesis discusses design of narrowband low noise amplifiers for multi¬standard applications. The target of this work is to design a low noise ampli¬fier(LNA) for DCS1800 and Bluetooth standard frequency bands. Various designs for narrowband multi-standard LNAs have been studied and a new design for tunable multi-standard LNA has been presented and designed using accumulation mode MOS varactors. As this design includes on-chip spiral inductors, the design, modelling and layout of on-chip inductors have been discussed briefly. The tool used for this purpose is ASITIC. Also ESD protection techniques for RF circuits and their effect on LNA per¬formance has been discussed. Finally fully differential LNA has been designed in O.35um AMS thick metal CMOS process using Cadence SpectreRF. The design also includes ESD pro¬tection at the input of LNA.

Dans l’industrie de la micro-électronique, les efforts à fournir pour les nouvelles applications développées deviennent de plus en plus contraignants et difficiles à supporter en terme de coût. Les agressions provenant des décharges électrostatiques (ESD) générées par l’environnement direct sur les puces constituent un facteur important de la chute de rendement et donc des coûts. Ces difficultés s’ajoutent aux limites physiques plus strictes pour fabriquer des transistors lorsque l’on aborde des échelles nanométriques. La technologie Silicium sur Isolant (SOI) a été développée afin de contourner cette difficulté, mais l’intégration des protections ESD limite son émergence du fait de la complexité de la mise au point et du développement d’un réseau de protection pour la puce.L’objectif annoncé de ce travail de recherche, effectué en collaboration entre STMicroelectronics le CEA et l’IMEP est d’évaluer les caractéristiques principales de la technologie pour la protection contre les décharges et de proposer une stratégie innovante de protection adaptée au SOI. En effet, à partir de résultats expérimentaux, nous avons pu constater que l’oxyde enterré, le BOX, limite les performances en robustesse et diminue la fenêtre de conception pour le déclenchement des protections. Pour y remédier, une structure commandée bidirectionnelle a été développée sur PDSOI afin de faciliter la dissipation thermique et améliorer la robustesse. Pour prolonger cette solution sur technologie FDSOI, une étude approfondie sur le thyristor afin a été menée afin de porter cette solution. L’analyse de simulation 3D et de résultats silicium ont permis de proposer une stratégie de protections innovantes pour le thyristor sur FDSOI. / In the microelectronics industry, the fabrication process for advanced technological nodes becomes more and more cumbersome and limiting in terms of cost. The electrostatic discharges (ESD) generated by the direct environment affect the circuits and constitute an important factor for the decrease of the yield and thus result in an increase of the costs. Apart from these difficulties, there are also issues arising from the physical limits of transistor integration when reaching the nanoscale.The Silicon on Insulator (SOI) technology was developed in order to bypass this difficulty. However, the integration of ESD protections limits its emergence due to the development complexity and the protection circuit needed. The goal of this work which was a collaboration between STMicroelectronics, CEA and IMEP was to evaluate the principal characteristics of this technology for electrostatic discharge protection and propose a novel protection strategy adapted for SOI.In fact, we were able to confirm from experimental results that the buried oxide (BOX) limits the performances in terms of robustness and narrows the window of conception for the triggering of the protections. A commanded bidirectional structure was developed on PDSOI and proposed as a solution to facilitate the thermal dissipation and improve the robustness.In order to extend this solution on FDSOI technology, a detailed study on the thyristor was performed. Analysis of the 3D simulations and experimental results permitted to propose an innovative strategy for ESD protections on FDSOI.

In the thesis the design of the Data Storage System (DSS) is proposed with the respect to the V-Model methodology. The design is based on users requirements, from which the system requirements are created and the technical specification of the DSS is developed. In the technical specifications the functionality of the DMM and HMI DSS subsystems are described and sub-system requirements are assigned to them, then they are subdivided and assigned to individual DMM (Data memory module) and HMI hardware items. Moreover, requirements are analyzed on hardware items, specific electronic components, are selected and implemented into the block design of the DMM hardware. Based on the block design of hardware, the hardware of the DMM subsystem is designed, selectively simulated and implemented along with the printed circuit board. On the implemented hardware of the DMM subsystems measurements are performed in order to verify the basic functionality of the hardware and the calculated, assimilated and measured values are compared as well. At the end of the thesis there is a short description of the implementation of the software design and its use for basic initialization of the selected processor, together with the verification of its basic function - measuring the frequency of the internal clock sources and the clock domains. The work is completed by sending a message of defined parameters to the selected communication line and sapling it by an oscilloscope, so that the basic function of the DMM subsystem is verified.

The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.