With the rapid increase in the density and the size of chips and systems, area and power dissipation become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power design techniques are essential for today's VLSI industry. The history of symbolic logic and some typical techniques for finite state machine (FSM) logic synthesis are reviewed. The state assignment is used to optimize area and power dissipation for FSMs. Two cost functions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to search for a good state assignment to minimize the cost functions. The algorithm has been implemented in C. The program can produce better results than NOVA, which is integrated into SIS by DC Berkeley, and other publications both in area and power tested by MCNC benchmarks. Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flops can save power for digital systems significantly. Three new kinds of flip-flops, called differential CMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valued flip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice. Most researchers have focused on developing low-power techniques in AND/OR or NAND & NOR based circuits. The low power techniques for AND /XOR based circuits are still in their early stage of development. To implement a complex function involving many inputs, a form of decomposition into smaller subfunctions is required such that the subfunctions fit into the primitive elements to be used in the implementation. Best polarity based XOR gate decomposition technique has been developed, which targets low power using Huffman algorithm. Compared to the published results, the proposed method shows considerable improvement in power dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller (FPRM) forms. Based on polarity transformation, an algorithm is developed and implemented in C language which can find the best polarity for power and area optimization. Benchmark examples of up to 21 inputs run on a personal computer are given.

It has been shown that the heati rate varies not only in relation to the cardiac demand but is also affected by the presence of cardiac disease and diabetes. Furthermore, it has been shown that heart rate variability may be used as an early indicator of cardiac disease susceptibility and the presence of diabetes. Therefore, the heati rate variability may be used for early clinical screening of these diseases. In order to reliably assess the patient's condition, the heati rate variability infolTIlation is determined from an electrocardiogram data acquisition system. Once collected, the heati rate variability signal is characterised and used as a basis for classification. This study details the development of a heart rate variability data acquisition system, method of collecting known patient data, and design of a signal-processing algorithm that characterises heart rate variability infolTIlation to be used as a basis for patient classification. Specifically, six sets of 5 minute electrocardiogram signals are collected by a personal computer based data acquisition system in a clinical setting. Consecutive R-wave deflections are detected from the electrocardiogram and used to determine the individual heart beat intervals. The outlying measurements are then removed and the remaining data is interpolated. The processed data is then characterised using timefrequency analysis and specific features are determined. Lastly, these features are used as a basis in a classification system. The results are then compared to the known patient conditions and the effectiveness of the screening procedure is determined.

Considerable progress has been made recently 1n the understanding of combinational logic optimization. Consequently a large number of university and industrial Electric Computing Aided Design (ECAD) programs are now available for optimal logic synthesis of combinational circuits. The progress with sequential logic synthesis and optimization, on the other hand, is considerably less mature. In recent years, evolutionary algorithms have been found to be remarkably effective way of using computers for solving difficult problems. This thesis is, in large part, a concentrated effort to apply this philosophy to the synthesis and optimization of sequential circuits. A state assignment based on the use of a Genetic Algorithm (GA) for the optimal synthesis of sequential circuits is presented. The state assignment determines the structure of the sequential circuit realizing the state machine and therefore its area and performances. The synthesis based on the GA approach produced designs with the smallest area to date. Test results on standard fmite state machine (FS:M) benchmarks show that the GA could generate state assignments, which required on average 15.44% fewer gates and 13.47% fewer literals compared with alternative techniques. Hardware evolution is performed through a succeSSlOn of changes/reconfigurations of elementary components, inter-connectivity and selection of the fittest configurations until the target functionality is reached. The thesis presents new approaches, which combine both genetic algorithm for state assignment and extrinsic Evolvable Hardware (EHW) to design sequential logic circuits. The implemented evolutionary algorithms are able to design logic circuits with size and complexity, which have not been demonstrated in published work. There are still plenty of opportunities to develop this new line of research for the synthesis, optimization and test of novel digital, analogue and mixed circuits. This should lead to a new generation of Electronic Design Automation tools.

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Electromagnetic interference (EMI) is an escalating concern in the modern electronic climate. As such it has become a critical area to consider when designing and packaging electronics. With the growing volume of electronic devices available and with processor frequencies increasing, the electromagnetic environment is becoming ever more congested. The need for adequate EMI shielding has become an essential consideration. The desire for high performance combined with reductions in size, weight and manufacturing cost suggests that polymers should be ideal materials for parts such as electronic housings. Unfortunately polymers generally do not provide shielding from electromagnetic waves. The research detailed in this thesis investigates the manufacture and testing of conductively filled poly(methyl methacrylate) (PMMA) composites. Samples of PMMA resin and various electrically conductive filler materials were manufactured. The processing methods, electrical properties and electromagnetic behaviour were all investigated. Composite polymer coatings were printed with a K-Control Coater and evaluated for surface resistivity and EMI shielding effectiveness. Samples were produced with a range of filler materials including nickel, carbon, copper/aluminium and silver coated glass spheres. Shielding effectiveness values of approximately 70 dB were obtained for coatings of PMMA filled with silver coated hollow glass microspheres. Attempts were made to produce an alternaalternative filler material by electroless nickel plating of expanded graphite powder. Successful plating was achieved using conventional methods of surface sensitisation of the graphite. This however resulted in agglomerations of the powder and a loss of the desired physical properties. Alternative thermal surface treatments proved to be unsuccessful in activating the graphite surface with no nickel deposition occurring. Furthermore, electroless nickel plating techniques were successfully utilised in the development of an alternative manufacturing process for producing electrically conductive PMMA composites which contained a reduced metallic content, in relation to a more traditional production technique. Plaques were manufactured by compression moulding of nickel plated PMMA granules. These were compared against samples manufactured with nickel powder mixed in a Brabender Plasti-Corder. The electroless plating method produced samples that outperformed the comparative method and were shown to contain a reduced metallic content. Shielding effectiveness of the electroless plated granule samples achieved approximately 34 dB compared to a maximum of only 2.5 dB for the Brabender compounded samples. Outwith these areas of empirical testing a computer model was produced to simulate the electromagnetic shielding behaviour of composite materials using Comsol Multiphysics. This model appears to successfully simulate the waveguide testing apparatus. However the theoretical conductivity values as calculated from effective media theory resulted in disproportionate shielding effectiveness values obtained. Further research into the electroless plated and compression moulded PMMA composites would be beneficial in order to fully optimise the process. Equally the theoretical model would require further investigating and validating before more accurate simulations could be achieved.

A novel design of a moving-coil transducer coupled with a low-hardness elastomer called “the gel surround” is presented in this thesis. This device is termed a “gel-type audio transducer”. The gel-type audio transducer has been developed to overcome the problems that conventional loudspeakers have suffered - that is, the problem with size of the audio device against the quality of sound at low frequency range. Therefore the research work presented herein aims to develop the “gel-type audio transducer” as a next-generation audio transducer for miniaturized woofers. The gel-type audio transducer consists of the magnetic and coil-drive plate assembly, and these parts are coupled by the gel surround. The transducer is driven by the electromagnetic conversion mechanism (a moving-coil transducer) and its output driving force can be greatly enhanced by applying the novel mechanism of the gel surround especially at low frequency range, resulting in the enhanced acoustic efficiency. The transducer can be attached to a stiff and light panel with both the optimized impedance matching and minimised wave collisions. The performance of the gel-type audio transducer is greatly influenced by the mass of the magnetic assembly and compliance of the “gel surround”. But as the size of the magnet and its weight have to be kept minimal for a miniaturisation of the device, the focus of the research is on the effect of the of the gel surround. As a result, the effect of the gel surround, made of the RTV (room-temperature vulcanising) silicone elastomer, TPE (thermoplastic elastomer), and the silicone foam, on generation of the output driving force, the energy transfer from the transducer to a panel to which the transducer is attached, and sound radiation from the vibrating panel, was investigated. This effect was studied by COMSOL multiphysics (FE analysis) and thereby, the simulated results were verified by experiments such as the laser scanning measurement, DMA (dynamic mechanical analyzer), and the acoustic test. Successful development of prototypes of the gel-type audio transducers, with an enhanced acoustic efficiency at reduced size and weight, was achieved. Implementation of the transducers into consumer applications was also demonstrated with their commercial values.

Reed-Muller algebraic techniques, as an alternative means in logic design, became more attractive recently, because of their compact representations of logic functions and yielding of easily testable circuits. It is claimed by some researchers that ReedMuller algebraic techniques are particularly suitable for arithmetic circuits. In fact, no practical application in this field can be found in the open literature. This project investigates existing Reed-Muller algebraic techniques and explores their application in arithmetic circuits. The work described in this thesis is concerned with practical applications in arithmetic circuits, especially for minimizing logic circuits at the transistor level. These results are compared with those obtained using the conventional Boolean algebraic techniques. This work is also related to wider fields, from logic level design to layout level design in CMOS circuits, the current leading technology in VLSI. The emphasis is put on circuit level (transistor level) design. The results show that, although Boolean logic is believed to be a more general tool in logic design, it is not the best tool in all situations. Reed-Muller logic can generate good results which can't be easily obtained by using Boolean logic. F or testing purposes, a gate fault model is often used in the conventional implementation of Reed-Muller logic, which leads to Reed-Muller logic being restricted to using a small gate set. This usually leads to generating more complex circuits. When a cell fault model, which is more suitable for regular and iterative circuits, such as arithmetic circuits, is used instead of the gate fault model in ReedMuller logic, a wider gate set can be employed to realize Reed-Muller functions. As a result, many circuits designed using Reed-Muller logic can be comparable to that designed using Boolean logic. This conclusion is demonstrated by testing many randomly generated functions. The main aim of this project is to develop arithmetic circuits for practical application. A number of practical arithmetic circuits are reported. The first one is a carry chain adder. Utilising the CMOS circuit characteristics, a simple and high speed carry chain is constructed to perform the carry operation. The proposed carry chain adder can be reconstructed to form a fast carry skip adder, and it is also found to be a good application for residue number adders. An algorithm for an on-line adder and its implementation are also developed. Another circuit is a parallel multiplier based on 5:3 counter. The simulations show that the proposed circuits are better than many previous designs, in terms of the number of transistors and speed. In addition, a 4:2 compressor for a carry free adder is investigated. It is shown that the two main schemes to construct the 4:2 compressor have a unified structure. A variant of the Baugh and Wooley algorithm is also studied and generalized in this work.

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In certain applications, AND/XOR (Reed-Muller), and ORlXNOR (Dual form of Reed-Muller) logic have shown some attractive advantages over the standard Sum of Products (SOP) and Product of Sums (POS). Bidirectional conversion algorithms between SOP and AND/XOR also between POS and ORlXNOR based on Sparse and partitioning techniques are presented for multiple output Boolean functions. The developed programs are tested for some benchmarks with up to 20 inputs and 40 outputs. A new direct method is presented to calculate the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) from the truth vector of the POS. Any Boolean function can be expressed by FPDRM forms. There are 211 polarities for an n-variable function and the number of sum terms depends on these polarities. Finding the best polarity is costly interims of CPU time, in order to search for the best polarity which will lead to the minimum number of sums for a particular function. Therefore, an algorithm is developed to compute all the coefficients of the Fixed Polarity Dual Reed-Muller (FPDRM) with polarity p from any polarity q. This technique is used to find the best polarity of FPDRM among the 211 fixed polarities. The algorithm is based on the Dual- polarity property and the Gray code strategy. Therefore, there is no need to start from POS form to find FPDRM coefficients for all the polarities. The proposed methods are efficient in terms of memory size and CPU time. A fast algorithm is developed and implemented in C language which can convert between POSs and FPDRMs. The program was tested for up to 23 variables. A modified version of the same program was used to find the best polarity. For up to 13 variables the CPU time was less than 42 seconds. To search for the optimal polarity for large number of variables and to reduce the se arch time 0 ffinding the 0 ptimal polarity 0 fthe function, two new algorithms are developed and presented in this thesis. The first one is used to convert between P OS and Positive Polarity Dual Reed-Muller (PPDRM) forms. The second algorithm will find the optimal fixed polarity for the FPDRM among the 211 different polarities for large n-variable functions. The most popular minimization criterion of the FPDRM form is obtained by the exhaustive search of the entire polarity vector. A non-exhaustive method for FPDRM expansions is presented. The new algorithms are based on separation of the truth vector (T) of POSs around each variable Xi into two groups. Instead of generating all of the polarity sets and searching for the best polarity, this algorithm will find the optimal polarity using the separation and sparse techniques, which will lead to optimal polarity. Time efficiency and computing speed are thus achieved in this technique. The algorithms don't require a large size of memory and don't require a long CPU time. The two algorithms are implemented in C language and tested for some benchmark. The proposed methods are fast and efficient as shown in the experimental results and can be used for large number of variables.