This thesis reports the development and analysis of high performance CMOS readout electronics for increasing the performance of MEMS gyroscopes developed at Middle East Technical University (METU). These readout electronics are based on unity gain buffers implemented with source followers. High impedance node biasing problem present in capacitive interfaces is solved with the implementation of a transistor operating in the subthreshold region. A generalized fully differential gyroscope model with force feedback electrodes has been developed in order to simulate the capacitive interfaces with the model of the gyroscope. This model is simplified for the single ended gyroscopes fabricated at METU, and simulations of resonance characteristics are done. Three gyroscope interfaces are designed by considering the problems faced in previous interface architectures. The first design is implemented using a single ended source follower biased with a subthreshold transistor. From the simulations, it is observed that biasing impedances up to several gigaohms can be achieved. The second design is the fully differential version of the first design with the addition of a self biasing scheme. In another interface, the second design is modified with an instrumentation amplifier which is used for fully differential to single ended conversion. All of these interfaces are fabricated in a standard 0.6 &micro / m CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(&deg / /sec) with a nonlinearity of only 0.001% in &plusmn / 100 &deg / /sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 &deg / /&amp / #8730 / hr and 124.7 &deg / /hr, respectively.

In this thesis, the VLSI implementation of Viterbi decoder using a design and simulation platform called SystemC is studied. For this purpose, the architecture of Viterbi decoder is tried to be optimized for VLSI implementations. Consequently, two novel area efficient structures for reconfigurable Viterbi decoders have been suggested. The traditional and SystemC design cycles are compared to show the advantages of SystemC, and the C++ platforms supporting SystemC are listed, installation issues and examples are discussed. The Viterbi decoder is widely used to estimate the message encoded by Convolutional encoder. For the implementations in the literature, it can be found that special structures called trellis have been formed to decrease the complexity and the area. In this thesis, two new area efficient reconfigurable Viterbi decoder approaches are suggested depending on the rearrangement of the states of the trellis structures to eliminate the switching and memory addressing complexity. The first suggested architecture based on reconfigurable Viterbi decoder reduces switching and memory addressing complexity. In the architectures, the states are reorganized and the trellis structures are realized by the usage of the same structures in subsequent instances. As the result, the area is minimized and power consumption is reduced. Since the addressing complexity is reduced, the speed is expected to increase. The second area efficient Viterbi decoder is an improved version of the first one and has the ability to configure the parameters of constraint length, code rate, transition probabilities, trace-back depth and generator polynomials.

This thesis study investigates the connection between design patterns, OO metrics and software error-proneness. The literature on OO metrics, design patterns and software error-proneness is reviewed. Different software projects and synthetic source codes have been analyzed to verify this connection.

In this thesis an integrated, dynamic model for cardiovascular and respiratory systems has been developed. Models of cardiopulmonary system, airway mechanics and gas exchange that preexisted in literature have been reviewed, modified and combined. Combined model composes the systemic and pulmonary circulations, left/right ventricles, tissue/lung compartments, airway/lung mechanics and gas transportation. Airway resistance is partitioned into three parts (upper, middle, small airways). A collapsible airways segment and a viscoelastic element describing lung tissue dynamics and a static chest wall compliance are included. Frank-Starling Law, Bowditch effect and variable cerebral flow are also employed in the model. The combined model predictions have been validated by laboratory data collected from two healthy, young, male subjects, by performing dynamic bicycle exercise tests, using Vmax 229 Sensormedics, Cardiopulmonary Exercise Testing Instrument. The transition from rest to exercise under a constant ergometric workload is simulated. The initial anaerobic energy supply, autoregulation and the dilatation of pulmonary vessels are considered. Mean arterial blood pressure and the blood gas concentrations are assumed to be regulated by the controllers of the central nervous system namely, the heart rate and alveolar ventilation. Cardiovascular and respiratory regulation is modeled by a linear feedback control which minimizes a quadratic cost functional.

Due to their programmable nature, Field Programmable Gate Arrays (FPGAs) offer a good test environment for reconfigurable systems. FPGAs can be reconfigured during the operation with changing demands. This feature, known as Runtime Reconfiguration (RTR), can be used to speed-up computations and reduce system cost. Moreover, it can be used in a wide range of applications such as adaptable hardware, fault tolerant architectures. This thesis is mostly concentrated on the runtime reconfigurable architectures. Critical properties of runtime reconfigurable architectures are examined. As a case study, a Triple Modular Redundant (TMR) system has been implemented on a runtime reconfigurable FPGA. The runtime reconfigurable structure increases the system reliability against faults. Especially, the weakness of SRAM based FPGAs against Single Event Upsets (SEUs) is eliminated by the designed system. Besides, the system can replace faulty elements with non-faulty elements during the operation. These features of the developed architecture provide extra safety to the system also prolong the life of the FPGA device without interrupting the whole system.

Coaxial-to-microstrip launcher and microstrip patch array antenna are designed to work at center frequency of 36.85 GHz with a bandwidth higher than 300 MHz. The antenna array design also includes the feeding network distributing the power to each antenna element. The design parameters are defined on this report and optimized by using an Electromagnetic Simulation software program. In order to verify the theoretical results, microstrip patch array antenna is produced as a prototype. Measurements of antenna parameters, electromagnetic field and circuit properties are interpreted to show compliance with theoretical results. The values of deviation between theoretical and experimental results are discussed as a conclusion.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

This thesis presents a novel monolithic phased array implemented using the RF MEMS technology. The structure, which is designed at 15 GHz, consists of four linearly placed microstrip patch antennas, 3-bit distributed RF MEMS low-loss phase shifters, and a corporate feed network. The RF MEMS phase shifter employed in the system consists of three sections with a total of 28 unit cells, and it occupies an area of 22.4 mm &amp / #61620 / 2.1 mm. The performance of the phase shifters is improved using high-Q metal-air-metal capacitors in addition to MEMS switches as loading elements on a high-impedance coplanar waveguide transmission line. The phased array is fabricated monolithically using an in-house surface micromachining process, where a 1.2-&amp / #61549 / m thick gold structural layer is placed on a 500-&micro / m thick glass substrate with a capacitive gap of 2 &amp / #61549 / m. The fabrication process is simple, requires only 6 masks, and allows the implementation of various RF MEMS components on the same substrate, such as RF MEMS switches and phase shifters. The fabricated monolithic phased array occupies an area of only 6 cm &amp / #61620 / 5 cm. The measurement results show that the phase shifter can provide nearly 20&amp / #61616 / /50&amp / #61616 / /95&amp / #61616 / phase shifts and their eight combinations at the expense of 1.5 dB average insertion loss at 15 GHz. The phase shifters can be actuated with 16 V, while dissipating negligible power due to its capacitive operation. It is also shown by measurements that the main beam can be steered to 4&amp / #61616 / and 14&amp / #61616 / by suitable settings of the RF MEMS phase shifters.

One of the goals of Electroencephalography (EEG) is to correctly localize brain activities by the help of voltage measurements taken on scalp. However, due to computational difficulties of the problem and technological limitations, the accuracy level of the activity localization is not perfect and should be improved. To increase accuracy level of the solution, realistic, i.e. patient dependent, head models should be created. Such head models are created via assigning realistic conductivity values of head tissues onto realistic tissue positions. This study initially focuses on obtaining patient dependent spatial information from T1-weighted Magnetic Resonance (MR) head images. Existing segmentation algorithms are modified according to our needs for classifying eye tissues, white matter, gray matter, cerebrospinal fluid, skull and scalp from volumetric MR head images. Determination of patient dependent conductivity values, on the other hand, is not considered as a part of this study, and isotropic conductivity values anticipated in literature are assigned to each segmented MR-voxel accordingly. Upon completion of the tissue classification, forward problem of EEG is solved using the Finite Difference (FD) method employing a realistic head model. Utilization of the FD method aims to lower computational complexity and to simplify the process of mesh creation for brain, which has a very complex boundary. Accuracy of the employed numerical method is investigated both on Electrical Impedance Tomography (EIT) and EEG forward problems, for which analytical solutions are available. The purpose of EIT forward problem integration into this study is to evaluate reciprocal solution of the EEG forward problem.

This thesis presents the design and implementation of a millimeter-wave Gunn diode oscillator operating at 35 GHz (Ka (R) 26.5-40 GHz Band). The aim of the study is to produce a high frequency, high power signal from a negative resistance device situated in a waveguide cavity by applying a direct current bias. First the physics of Gunn diodes is studied and the requirements that Gunn diode operates within the negative differential resistance region is obtained. Then the best design configuration is selected. The design of the oscillator includes the design of the waveguide housing, diode mounting and the bias insertion network. Some simulation tools are used to predict, approximately, the behaviour of the oscillator and the bias coupling circuit. For tuning purposes, a sliding backshort and a triplescrew- tuner system is used. For different bias values and different positions of the tuning elements oscillations are observed. A much more stable and higher magnitude oscillations were obtained with the inclusion of &ldquo / resonant disc&rdquo / placed on top of the diode. 15 dBm power was measured at a frequency of 28 GHz. Laboratory measurements have been carried out to determine the oscillator frequency, power output and stability for different bias conditions.