This thesis study presents design and SystemC implementation of a Crypto Processor for Advanced Encryption Standard (AES), Data Encryption Standard (DES) and Triple DES (TDES) algorithms. All of the algorithms are implemented in single architecture instead of using separate architectures for each of the algorithm. There is an Instruction Set Architecture (ISA) implemented for this Crypto Processor and the encryption and decryption of algorithms can be performed by using the proper instructions in the ISA. A permutation module is added to perform bit permutation operations, in addition to some basic structures of general purpose micro processors. Also the Arithmetic Logic Unit (ALU) structure is modified to process some crypto algorithm-specific operations. The design of the proposed architecture is studied using SystemC. The architecture is implemented in modules by using the advantages of SystemC in modular structures. The simulation results from SystemC are analyzed to verify the proposed design. The instruction sets to implement the crypto algorithms are presented and a detailed hardware synthesis study has been carried out using the tool called SystemCrafter.

This thesis investigates the variations of electrical properties of linear antennas mounted on certain platforms, depending on the physical properties of that platform. In this respect, related basic antenna simulations, electromagnetic simulations from primitive to complex models of airframes, and scale model measurements were used. Firstly, electrical properties of monopoles at known environment were examined and basic analyses were performed via an electromagnetic simulation tool, named CST Microwave Studio&reg / . In addition, important aspects of simulation tool were investigated. Then, an F-4 aircraft model was used to observe the electrical characteristics of antennas mounted on it. Using 3D model of F-4 aircraft, realistic antenna placement points were assigned and monopoles were attached to those points. Alternatively, a simplified F-4 model was also used and for two different models, identical simulations were done, followed by accuracy and performance analysis between the results obtained from simplified and exact models. As the outcome of these simulations, certain parameters like impedance, antenna-to-antenna coupling and radiation pattern values were examined. Additionally, change in antennas&rsquo / electrical characteristics due to their position over the airframe was investigated. In addition, a 1:10 down-scaled and copper-plated F-4 aircraft model was obtained and equipped with identical antennas. By using the measurements done on this scale model, antenna-to-antenna coupling results of MWS&reg / were verified by measurements. Finally, advantages and disadvantages of using electromagnetic simulation tools and scale model measurements for such antenna studies were discussed.

In this thesis, co-design and co-verification of a microcontroller hardware and software using SystemC is studied. For this purpose, an MC68HC11 microcontroller unit, a test bench that contains input and output modules for the verification of microcontroller unit are implemented using SystemC programming language and a visual simulation program is developed using C# programming language in Microsoft .NET platform. SystemC is a C++ class library that is used for co-designing hardware and software of a system. One of the advantages of using SystemC in system design is the ability to design each module of the system in different abstraction levels. In this thesis, test bench modules are designed in a high abstraction level and microcontroller hardware modules are designed in a lower abstraction level. At the end, a simulation platform that is used for co-simulation and co-verification of hardware and software modules of overall system is developed by combining microcontroller implementation, test bench modules, test software and visual simulation program. Simulations at different levels are performed on the system in the developed simulation platform. Simulation results helped observing errors in designed modules easily and making corrections until all results verified designed hardware modules. This stuation showed that co-designing and co-verifying hardware and software of a system helps finding errors and making corrections in early stages of system design cycle and so reducing design time of the system.

Range and Doppler measurement of targets for medium PRF radars is handicapped by folding and blind regions. This requires use of multiple PRFs and a resolver algorithm. The aim of the thesis is to develop various algorithms for the task and estimate their performance. Four different range and Doppler resolver algorithms and a test software is developed by using Matlab &reg / GUI and their performances due to the selected radar parameters in a multi- target environment are examined.

In this study, delay-insensitive asynchronous circuit design style has been adopted to systolic array architectures to exploit the benefits of both techniques for improved throughput. A delay-insensitivity verification analysis method employing symbolic delays is proposed for bit-level pipelined asynchronous circuits. The proposed verification method allows datadependent early output evaluation to co-exist with robust delay-insensitive circuit behavior in pipelined architectures such as systolic arrays. Regardless of the length of the pipeline, delay-insensitivity verification of a systolic array with early output evaluation paths in onedimension is reduced to analysis of three adjacent systoles for eight possible early/late output evaluation scenarios. Analyzing both combinational and sequential parts concurrently, delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing constraints on the environment / the method is technology independent and robust against all physical and environmental variations. To demonstrate the verification method, adders are selected for being at the core of data processing systems. Two asynchronous adder topologies in the delay-insensitive dual-rail threshold logic style, having data-dependent early carry evaluation paths, are converted into bit-level pipelined systolic arrays. On these adders, data-dependent delay-insensitivity violations are detected and resolved using the proposed verification technique. The modified adders achieved the targeted O(log2n) average completion time and -as a result of bit-level pipelining- nearly constant throughput against increased bit-length. The delay-insensitivity verification method could further be extended to handle more early output evaluation paths in multi-dimension.

Electrocardiography (ECG) is the most important noninvasive tool used for diagnosing heart diseases. An ECG interpretation program can help the physician state the diagnosis correctly and take the corrective action. Detection of the QRS complexes from the ECG signal is usually the first step for an interpretation tool. The main goal in this thesis was to develop robust and high performance QRS detection algorithms, and using the results of the QRS detection step, to classify these beats according to their different pathologies. In order to evaluate the performances, these algorithms were tested and compared in Massachusetts Institute of Technology Beth Israel Hospital (MIT-BIH) database, which was developed for research in cardiac electrophysiology. In this thesis, four promising QRS detection methods were taken from literature and implemented: a derivative based method (Method I), a digital filter based method (Method II), Tompkin&rsquo / s method that utilizes the morphological features of the ECG signal (Method III) and a neural network based QRS detection method (Method IV). Overall sensitivity and positive predictivity values above 99% are achieved with each method, which are compatible with the results reported in literature. Method III has the best overall performance among the others with a sensitivity of 99.93% and a positive predictivity of 100.00%. Based on the detected QRS complexes, some features were extracted and classification of some beat types were performed. In order to classify the detected beats, three methods were taken from literature and implemented in this thesis: a Kth nearest neighbor rule based method (Method I), a neural network based method (Method II) and a rule based method (Method III). Overall results of Method I and Method II have sensitivity values above 92.96%. These findings are also compatible with those reported in the related literature. The classification made by the rule based approach, Method III, did not coincide well with the annotations provided in the MIT-BIH database. The best results were achieved by Method II with the overall sensitivity value of 95.24%.

Gun and gun turret systems are the primary units of the weapon systems of an aircraft. They are required to hit targets accurately during operations. That is why a complete, high precision control of weapon systems is required. This function is provided by accurate modeling of the system and the design of a suitable controller. This study presents the modeling of and controller design for the gun and turret system for an aircraft. For the controller design purpose, first the mathematical model of the system is constructed. Then the controller is designed to position the turret system as the target comes into sight. The reference input to the controller will either be obtained from a FLIR (Forward Looking Infrared) unit or from a HCU (Hand Control Unit). The basic specification for the controller is to hold theerror signal within the 5.5&deg / positioning envelope. This specification is satisfied by designing Linear Quadratic Gaussian and Internal Model Control type controllers. The performance of the overall system has been examined both by simulation studies and on the real physical system. Results have shown that the designed system is well over being sufficient.

This thesis presents the theory, design, fabrication, and measurement results of novel reconfigurable impedance tuner, phase shifter, and vector modulators using the RF MEMS technology. The presented circuits are based on triple stub topology, and it is shown both theoretically and experimentally in this thesis that it is possible to control the insertion phase and amplitude of the input signal simultaneously using this topology. The presented circuits are implemented using an in-house, surface micromachining fabrication process developed at METU, namely METU RF MEMS Fabrication Process, which is implemented using six masks on quartz substrates. The RF MEMS impedance tuner is designed to operate in 6-20 GHz frequency band, and it covers the Smith Chart with 1331 impedance points. The measurement results of 729 impedance points of the fabricated impedance tuner show that a wide Smith Chart coverage is obtained in the entire band. The RF MEMS phase shifter is designed to cover 0-360 degrees range 10 degree steps at 15 GHz center frequency. The measurement results of the fabricated phase shifter show that the average phase error is 1.7 degrees, the average insertion loss is -3.1 dB, and the average return loss is -19.3 dB for the measured 21 phase states. The phase shifter can also work up to 30 GHz and 40 GHz with average insertion losses of -5 dB and -8 dB, respectively. The designed RF MEMS vector modulator operates in 22.5-27.5 GHz band, and it has 3 amplitude and 8 phase states. The measurement results of the fabricated vector modulator show that the amplitude error is 0.5 dB, the phase error is 4 degrees, and the return loss is -15 dB on average among the 24 measured states at each of 22.5, 25, and 27.5 GHz frequencies.

Designing smarter vehicles, aiming to minimize the number of driverbased wrong decisions or accidents, which can be faced with during the drive, is one of hot topics of today&rsquo / s automotive technology. In the design of smarter vehicles, several research issues can be addressed / one of which is Traffic Sign Recognition (TSR). In TSR systems, the aim is to remind or warn drivers about the restrictions, dangers or other information imparted by traffic signs, beforehand. Since the existing signs are designed to draw drivers&rsquo / attention by their colors and shapes, processing of these features is one of the crucial parts in these systems. In this thesis, a Traffic Sign Recognition System, having ability of detection and identification of traffic signs even with bad visual artifacts those originate from some weather conditions or other circumstances, is developed. The developed algorithm in this thesis, segments the required color influenced by the illumination of the environment, then reconstructs the shape of partially occluded traffic sign by its remaining segments and finally, identifies it. These three stages are called as &ldquo / Segmentation&rdquo / , &ldquo / Reconstruction&rdquo / and &ldquo / Identification&rdquo / respectively, within this thesis. Due to the difficulty of analyzing partial segments to construct the main frame (a whole sign), the main complexity of the algorithm takes place in the &ldquo / Reconstruction&rdquo / stage.

In this thesis, real time image rendering for hand held devices is studied according to user&rsquo / s view point choice and using image frames with corresponding depth maps obtained from 2 different cameras, of which positions on coordinate system is known. User&rsquo / s view point choice is restricted to the area between right, and left cameras. Occlusion handling methods for image rendering systems is explored and discussed together with frame enhancement techniques. Median filtering is studied for multicolor image frames and post processing methods are discussed for image enhancement at the end of rendering algorithm. In this thesis, OMAP3530 microprocessor is used as the main processor which processes suggested rendering algorithm with occlusion handling and frame enhancement. proposed algorithms are implemented on DSP core and ARM cores of OMAP3530 separately and their performances are evaluated through experiments. Embedded Linux (Kernel-2.6.22) is run as the operating system for applications. Driver usage together with devices for Linux embedded operating system is explored and studied. 3 boards are used for the realization of proposed system. OMAP35x EVM board from Mistral Solutions Company is used for processor utilization, high resolution LCD utilization, system monitoring, user interface and communication purposes. Two daughter cards are designed for user view point determination. First daughter card handles communication process with EVM board and calculates view point according to input from second daughter card with single axis response GYRO sensor (ADIS16060). Spartan&reg / -3A DSP FPGA family is utilized in this system for view point determination. DSP slices that are hardly present inside gate arrays of this FPGA family are utilized and their performance is studied. Asynchronous memory interface, i2c bus interface, SPI interface are studied and implemented on FPGA.