No description available.

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of test bench development. Two approaches being explored are: 1) behavioral - the CASE tools develop complete high level models of the test bench, and 2) structural- a library of primitive components is developed so that a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to construct the test bench. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source. The objective of this thesis is the development of a set of library models from which a structural test bench can be created. This thesis also describes creation of the structural test bench using the library of primitive components and Synopsys Graphical Environment, a conventional schematic capture tool. This approach has been implemented for two applications: 1) A 2D Image processing algorithm - InfraRed Search and Track (IRST) and 2) Synthetic Aperture Radar (SAR). An intelligent interface developed in C combines the structural model with user information which provides for generics and inputs. This thesis also shows how a requirements capture tool can be used to generate generic values. / Master of Science

No description available.

The aim of this thesis is a preliminary draft of test equipment for testing fuel injectors Common Rail system with the drive shaft radial loading. The work presents a brief overview of the contemporary designs of the pump system, which then leads on equipment design.

Validating DSP circuits modeled in VHDL involves generating test data, creating VHDL test benches, and simulating the test benches including models under test (MUTs). This is a laborious and time-consuming process. Therefore, it is desirable to develop a high level approach to automating and planning these tasks. This dissertation presents a high level test planning system for functional validation of VHDL DSP models. The system requirements parameterized from the specifications constitute the input space and serve as generics of test benches. Library-based test benches are developed using high level design tools. A test planning framework uses a goal tree structure as a vehicle of planning and documenting the testing activities. In a goal tree, test goals are given based on the specifications and test groups are defined to satisfy the test goals. Test groups partially constrain the system requirements and thus partition the input space into smaller and more manageable subspaces. A set of test strategies are then applied to the test groups for efficient test case design. Each test case is mapped to a configuration declaration of the test bench. The test bench is then simulated to generate test vectors against which the MUT is tested. The MUT response is compared with the gold response by a comparator and verdicts are reached by test oracles. An integrated test planning software system has been developed for test planning and test automation based on this approach. As an illustration of this approach, this dissertation uses the Synthetic Aperture Radar system as a case study. Completeness and effectiveness of the generated test set are evaluated. This dissertation also discusses approaches to hierarchical faulty module isolation for hierarchical circuits. Exposability is proposed to measure the extent that signal values are revealed to the tester and is used as the cost function for the faulty module search problem. An expanded goal tree which explores the functional and structural aspects of a hierarchical circuit is also presented. / Ph. D.

Test plans are used to guide, organize and document the testing activities during hardware design process. Manual test planning and configuration is known to be labor intensive, time consuming and error prone. It is desirable to develop efficient approaches to model testing and to develop test tools to automate test-planning activities. With the emergence of new hardware design paradigms, there is a need to develop more specialized description languages. However, adopting a new language for hardware-based designs involves adapting the existing design and verification tool suite for the new language. This is a very time consuming and capital intensive process. To ease the adoption of new description languages, it is desirable to develop multi-language support methodologies for design and test tools. This thesis addresses a subset of these problems. It presents a goal-tree based test methodology which is very effective for functional testing of hardware models in multiple application domains. Then it describes an approach for achieving a high degree of language independence using ideas of data abstraction. It also presents an automated test-planning tool called the "Goal Tree System (GTS)", which provides an implementation of goal tree methodology and multi-language support ideas. We demonstrate the use of this tool by testing models developed in VHDL and SystemC. We also present the design aspects of the Goal Tree System, which enable it to work across multiple platforms and with multiple simulators. / Master of Science

Syftet med arbetet var att undersöka möjligheten att utveckla en testbänk som kan underlätta felsökning och testning till fem olika ECU:er. 93 utgångar, bland annat DAC:ar, digitala- och frekvensutgångar finns med i kravspecifikationerna. Dessa utgångar styrs utifrån paneler i CANalyzer med hjälp av programmering i Arduino och CANalyzers egna språk CAPL. Testbänken visar goda resultat och har fått positiv respons från företaget, den levererar de förväntade värdena på samtliga 93 utgångar med en felmarginal på max 3%. Det finns begränsningar med att bygga denna typ av testbänk kopplade till komponentval, tid och resurser.

The paper presents design solution and physical implementation of a system for examination of electro hydraulic steering based on OSPE 200 components. The implementation is based on synthesis of required hydraulic and structure parameters, presented in a previous paper. Now we present the interconnection of the digital control system and the closed-loop flow diagram. A formal description of embedded software is presented too, which supports operation of PI control algorithm in real-time. Identification is performed based on experimentally reported the transitional process by developing mathematical models. Presents the structure and capabilities of the models for identification, as well as procedures for their validation.

Après le lancement du premier satellite artificiel en 1957, l'évolution de diverses technologies a favorisé la miniaturisation des satellites. En 1999, le développement des nano-satellites modulaires appelés CubeSats, qui ont la forme d'un cube d'un décimètre de côté et une masse de 1 kg à 10 kg, a été initié par un effort commun de l'Université polytechnique de Californie et de l'Université de Stanford. Depuis lors, grâce à l’utilisation de composants électroniques standards à faible coût, les CubeSats se sont largement répandus.Au cours des dernières années, le nombre de CubeSats lancés a régulièrement augmenté, mais moins de la moitié des missions ont atteint leurs objectifs. L'analyse des défaillances des CubeSats montre que la cause la plus évidente est le manque d’essais adéquats des composants du système ou du système au complet. Parmi les tâches particulièrement difficiles, on compte les essais « hardware-in-the-loop » (HIL) du système de contrôle d'attitude et d'orbite (SCAO) d’un CubeSat. Un système dédié à ces essais doit permettre des simulations fiables de l'environnement spatial et des mouvements réalistes des CubeSats. La façon la plus appropriée d’obtenir de telles conditions d’essai repose sur l’utilisation d’un coussin d'air. Toutefois, les mouvements du satellite sont alors contraints par les limites géométriques, qui sont inhérentes aux coussins d'air. De plus, après 15 années de développements de CubeSats, la liste des systèmes proposés pour tester leur SCAO reste très limitée.Aussi, cette thèse est consacrée à l’étude et à la conception d’un système robotique innovant pour des essais HIL du SCAO d’un CubeSat. La nouveauté principale du système d'essai proposé est l’usage de quatre coussins d'air au lieu d'un seul et l’emploi d’un robot manipulateur. Ce système doit permettre des mouvements non contraints du CubeSat. Outre la conception du système d'essai, cette thèse porte sur les questions liées: (i) à la détermination de l'orientation d’un CubeSat au moyen de mesures sans contact; (ii) au comportement de l’assemblage des coussins d'air; (iii) à l'équilibrage des masses du système.Afin de vérifier la faisabilité de la conception proposée, un prototype du système d'essai a été développé et testé. Plusieurs modifications destinées à en simplifier la structure et à réduire le temps de fabrication ont été effectuées. Un robot Adept Viper s650 est notamment utilisé à la place d'un mécanisme sphérique spécifiquement conçu. Une stratégie de commande est proposée dans le but d’assurer un mouvement adéquat du robot qui doit suivre les rotations du CubeSat. Finalement, les résultats obtenus sont présentés et une évaluation globale du système d'essai est discutée. / After the launch of the first artificial Earth satellite in 1957, the evolution of various technologies has fostered the miniaturization of satellites. In 1999, the development of standardized modular satellites with masses limited to a few kilograms, called CubeSats, was initiated by a joint effort of California Polytechnic State University and Stanford University. Since then, CubeSats became a widespread and significant trend, due to a number of available off-the-shelf low cost components.In last years, the number of launched CubeSats constantly grows, but less than half of all CubeSat missions achieved their goals (either partly or completely). The analysis of these failures shows that the most evident cause is a lack of proper component-level and system-level CubeSat testing. An especially challenging task is Hardware-In-the-Loop (HIL) tests of the Attitude Determination and Control System (ADCS). A system devoted to these tests shall offer reliable simulations of the space environment and allow realistic CubeSat motions. The most relevant approach to provide a satellite with such test conditions consists in using air bearing platforms. However, the possible satellite motions are strictly constrained because of geometrical limitations, which are inherent in the air bearing platforms. Despite 15 years of CubeSat history, the list of the air bearing platforms suitable for CubeSat ADCS test is very limited.This thesis is devoted to the design and development of an air bearing testbed for CubeSat ADCS HIL testing. The main novelty of the proposed testbed design consists in using four air bearings instead of one and in utilizing a robotic arm, which allows potentially unconstrained CubeSat motions. Besides the testbed design principle, this thesis deals with the related issues of the determination of the CubeSat orientation by means of contactless measurements, and of the behavior of the air bearings, as well as with the need of a mass balancing method.In order to verify the feasibility of the proposed design, a prototype of the testbed is developed and tested. Several modifications aimed at simplifying the structure and at shortening the fabrication timeline have been made. For this reason, the Adept Viper s650 robot is involved in place of a custom-designed 4DoF robotic arm. A control strategy is proposed in order to provide the robot with a proper motion to follow the CubeSat orientation. Finally, the obtained results are presented and the overall assessment of the proposed testbed is put into perspective.

<p>This thesis describes the VHDL behavioral model design of a DSP On Chip Emulation Unit. The prototype of this design is the OnCE port of the Motorola DSP56002. </p><p>Capabilities of this On Chip Emulation Unit are accessible through four pins, which allows the user to step through a program, to set the breakpoint that stop program execution at a specific address, and to examine the contents of registers, memory, and pipeline information. The detailed design that includes input/output signals and sub blocks is presented in this thesis. </p><p>The user will interact with the DSP through a GUI on the host computer via the RS232 port. An interface between the RS232 and On Chip Emulation Unit is therefore designed as well. </p><p>The functionality is designed to be same as described by Motorola and it is verified by a test bench. The writing of the test bench, test sequence and results is presented also.</p>