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This study concerns with the testing methods for mechanical characterization at micron scale. The need for the study arises from the fact that the mechanical properties of materials at micron scale differ compared to their bulk counterparts, depending on the microfabrication method involved. Various test structures are designed according to the criteria specified in this thesis, and tested for this purpose in micron scale. Static and fatigue properties of the materials are aimed to be extracted through the tests. Static test structures are analyzed using finite elements method in order to verify the results. Test structures were fabricated by deep reactive ion etching of 100 &micro / m thick (111) silicon and electroplating 18 &micro / m nickel layer. Performance of the test structures are evaluated based on the results of tests conducted on the devices made of (111) v silicon. According to the results of the tests conducted on (111) silicon structures, elastic modulus is found to be 141 GPa on average. The elastic modulus of electroplated nickel is found to be 155 GPa on average, using the same test structures. It is observed that while the averages of the test results are acceptable, the deviations are very high. This case is related to fabrication faults in general. In addition to the tests, a novel computer script utilizing image processing is also developed and used for determination of the deflections in the test structures.

abstract: A Single Event Transient (SET) is a transient voltage pulse induced by an ionizing radiation particle striking a combinational logic node in a circuit. The probability of a storage element capturing the transient pulse depends on the width of the pulse. Measuring the rate of occurrence and the distribution of SET pulse widths is essential to understand the likelihood of soft errors and to develop cost-effective mitigation schemes. Existing research measures the pulse width of SETs in bulk Complementary Metal-Oxide-Semiconductor (CMOS) and Silicon On Insulator (SOI) technologies, but not on Fin Field-Effect Transistors (FinFETs). This thesis focuses on developing a test structure on the FinFET process to generate, propagate, and separate SETs and build a time-to-digital converter to measure the pulse width of SET. The proposed SET test structure statistically separates SETs generated at NMOS and PMOS based on the difference in restoring current. It consists of N-collection devices to collect events at NMOS and P-collection devices to collect events at PMOS. The events that occur in PMOS of the N-collection device and NMOS of the P-collection device are false events. The logic gates of the collection devices are skewed to perform pulse expansion so that a minimally sustained SET propagates without getting suppressed by the contamination delay. A symmetric tree structure with an S-R latch event detector localizes the location of the SET. The Cartesian coordinates-based pulse injection structure injects external pulses at specific nodes to perform instrumentation and calibrate the measurement. A thermometer-encoded chain (vernier chain) with mismatched delay paths measures the width of the SET. For low Linear Energy Transfer (LET) tests, the false events are entirely masked and do not propagate since the amount of charge that has to be deposited for successful event propagation is significantly high. In the case of high LET tests, the actual events and false events propagate, but they can be separated based on the SET location and the width of the output event. The vernier chain has a high measurement resolution of ~3.5ps, which aids in separating the events. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2020

Les études qui seront présentées dans le cadre de cette thèse portent sur le développement et l’optimisation des techniques pour la modélisation compacte des transistors bipolaires à hétérojonction (TBH). Ce type de modélisation est à la base du développement des bibliothèques de composants qu’utilisent les concepteurs lors de la phase de simulation des circuits intégrés. Le but d’une technologie BiCMOS est de pouvoir combiner deux procédés technologiques différents sur une seule et même puce. En plus de limiter le nombre de composants externes, cela permet également une meilleure gestion de la consommation dans les différents blocs digitaux, analogiques et RF. Les applications dites rapides peuvent ainsi profiter du meilleur des composants bipolaires et des transistors CMOS. Le défi est d’autant plus critique dans le cas des applications analogiques/RF puisqu’il est nécessaire de diminuer la puissance consommée tout en maintenant des fréquences de fonctionnement des transistors très élevées. Disposer de modèles compacts précis des transistors utilisés est donc primordial lors de la conception des circuits utilisés pour les applications analogiques et mixtes. Cette précision implique une étude sur un large domaine de tensions d’utilisation et de températures de fonctionnement. De plus, en allant vers des nœuds technologiques de plus en plus avancés, des nouveaux effets physiques se manifestent et doivent être pris en compte dans les équations du modèle. Les règles d’échelle des technologies plus matures doivent ainsi être réexaminées en se basant sur la physique du dispositif. Cette thèse a pour but d’évaluer la faisabilité d’une offre de modèle compact dédiée à la technologie avancée SiGe TBH de chez ST Microelectronics. Le modèle du transistor bipolaire SiGe TBH est présenté en se basant sur le modèle compact récent HICUMversion L2.3x. Grâce aux lois d’échelle introduites et basées sur le dessin même des dimensions du transistor, une simulation précise du comportement électrique et thermique a pu être démontrée.Ceci a été rendu possible grâce à l’utilisation et à l’amélioration des routines et méthodes d’extraction des paramètres du modèle. C’est particulièrement le cas pour la détermination des éléments parasites extrinsèques (résistances et capacités) ainsi que celle du transistor intrinsèque. Finalement, les différentes étapes d’extraction et les méthodes sont présentées, et ont été vérifiées par l’extraction de bibliothèques SPICE sur le TBH NPN Haute-Vitesse de la technologie BiCMOS avancée du noeud 55nm, avec des fréquences de fonctionnement atteignant 320/370GHz de fT = fmax. / The aim of BiCMOS technology is to combine two different process technologies intoa single chip, reducing the number of external components and optimizing power consumptionfor RF, analog and digital parts in one single package. Given the respectivestrengths of HBT and CMOS devices, especially high speed applications benefit fromadvanced BiCMOS processes, that integrate two different technologies.For analog mixed-signal RF and microwave circuitry, the push towards lower powerand higher speed imposes requirements and presents challenges not faced by digitalcircuit designs. Accurate compact device models, predicting device behaviour undera variety of bias as well as ambient temperatures, are crucial for the development oflarge scale circuits and create advanced designs with first-pass success.As technology advances, these models have to cover an increasing number of physicaleffects and model equations have to be continuously re-evaluated and adapted. Likewiseprocess scaling has to be verified and reflected by scaling laws, which are closelyrelated to device physics.This thesis examines the suitability of the model formulation for applicability to production-ready SiGe HBT processes. A derivation of the most recent model formulationimplemented in HICUM version L2.3x, is followed by simulation studies, whichconfirm their agreement with electrical characteristics of high-speed devices. Thefundamental geometry scaling laws, as implemented in the custom-developed modellibrary, are described in detail with a strong link to the specific device architecture.In order to correctly determine the respective model parameters, newly developed andexisting extraction routines have been exercised with recent HBT technology generationsand benchmarked by means of numerical device simulation, where applicable.Especially the extraction of extrinsic elements such as series resistances and parasiticcapacitances were improved along with the substrate network.The extraction steps and methods required to obtain a fully scalable model library wereexercised and presented using measured data from a recent industry-leading 55nmSiGe BiCMOS process, reaching switching speeds in excess of 300GHz. Finally theextracted model card was verified for the respective technology.