Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices. / text

<p>Since the discovery of graphene, two-dimensional (2D) materials have attracted broad interests for transistor applications due to their atomically thin nature. This thesis studies nano-transistors based on 2D materials for several novel applications, including tunneling transistors for low-power electronics and reconfigurable transistors for hardware security.</p><p>The first part of the thesis focuses on tunneling field-effect transistors (TFETs). Since the current injection in a conventional MOSFET depends on thermionic injection over a gate-controlled barrier, the subthreshold swing (SS) of MOSFET is fundamentally limited to 60 mV/dec at room temperature, hindering the supply voltage scaling of integrated circuits (ICs). Utilizing band-to-band tunneling (BTBT) as current injection mechanism, TFETs overcome the SS limit by filtering out the Fermi tail in the source and achieve steep-slope switching. However, existing demonstrations of TFETs are plagued by low on-currents and degraded SS, largely due to the large tunneling distances caused by non-scaled body thicknesses, making 2D materials a promising candidate as channel materials for TFETs. In this thesis, we demonstrate a prototype TFET based on black phosphorus (BP) adopting electrostatic doping that is tuned by multiple top-gates, which allows the device to be reconfigured into multiple operation modes. The band-to-band tunneling mechanism is further confirmed by source-doping-dependent and temperature-dependent measurements, and the performance improvement of BP TFETs with further body and oxide thicknesses scaling is projected by atomistic simulation. In addition, a vertical BP TFET with a large tunneling area is also demonstrated, and negative differential resistance (NDR) is observed in the device.</p><p>The second part of the thesis focuses on reconfigurable nano-transistors with tunable p- and n-type operations and the implementation of hardware security based on such transistors. Polymorphic gate has been proposed as a hardware security primitive to protect the intellectual property of ICs from reverse engineering, and its operation requires transistors that can be reconfigured between p-type and n-type. However, a traditional CMOS transistor relies on substitutional doping, and thus its polarity cannot be altered after the fabrication. By contrast, 2D nano-transistors can attain both electron and hole injections. In this thesis, we review the Schottky-barrier injection in 2D transistors and demonstrate the feasibility of achieving complementary p-type and n-type transistors using BP as channel material by adopting metal contacts with different work functions. In this design, however, the discrepancy in the p-FET and n-FET device structures makes it unsuitable for reconfigurable transistors. Therefore, we continue to modify the device design to enable reconfigurable p-type and n-type operations in the same BP transistor. Finally, a NAND/NOR polymorphic gate is experimentally demonstrated based on the reconfigurable BP transistors, showing the feasibility of using 2D materials to enable hardware security.</p><p>In the last part, we demonstrate an artificial sub-60 mV/dec switching in a metal-insulator-metal-insulator-semiconductor (MIMIS) transistor. Negative capacitance FETs (NC-FETs) have attracted wide interest as promising candidates for steep-slope devices. However, the detailed mechanisms of the observed steep-slope switching are under intense debate. We show that sub-60 mV/dec switching can be observed in a WS2 transistor with an MIMIS structure – without any ferroelectric component. Using a resistor-capacitor (RC) network model, we show that the observed steep-slope switching can be attributed to the internal gate voltage response to the chosen varying gate voltage scan rates. Our results indicate that the measurement-related artefacts can lead to observation of sub-60 mV/dec switching and that experimentalists need to critically assess their measurement setups.</p>