Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. In this dissertation, thermal stresses and interfacial reliability of TSV structures are analyzed by combining analytical and numerical models with experimental measurements. First, three-dimensional near-surface stress distribution is analyzed for a simplified TSV structure consisting of a single via embedded in a silicon (Si) wafer. A semi-analytic solution is developed and compared with finite element analysis (FEA). For further study, the effects of anisotropic elasticity in Si and metal plasticity in the via on the stress distribution and deformation are investigated. Next, by micro-Raman spectroscopy and bending beam technique, experimental measurements of the thermal stresses in TSV structures are conducted. The micro-Raman measurements characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the bending beam technique measures the average stress and viii deformation in the TSV structures. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias is analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. To study the impacts of the thermal stresses on interfacial reliability of TSV structures, an analytical solution is developed for the steady-state energy release rate as the upper bound of the driving force for interfacial delamination. The effect of crack length and wafer thickness on the energy release rate is studied by FEA. Furthermore, to model interfacial crack nucleation, an analytical approach is developed by combining a shear lag model with a cohesive interface model. Finally, the effects of structural designs and the variation of the constituent materials on TSV reliability are investigated. The steady state solutions for the energy release rate are developed for various TSV designs and via materials (Al, Cu, Ni, and W) to evaluate the interfacial reliability. The parameters for TSV design optimization are discussed from the perspectives of interfacial reliability. / text

This study focused on the development and evaluation of die-attach material and substrate technology for high-temperature applications. For the die-attach material, a low-temperature sintering technique enabled by a nanoscale silver paste was developed for attaching large-area (>100 mm2) semiconductor chips. The nanoscale silver paste can be sintered at a much lower temperature (<300 oC) than in the conventional sintering process (>800 oC), and at the same time reached about 80 vol% bulk density. Analyses of the sintered joints by scanning acoustic imaging and electron microscopy showed that the attachment layer had a uniform microstructure with micron-sized porosity with the potential for high reliability under high temperature applications. We also investigated the effects of a large temperature cycling range on the reliability of direct bonded aluminum (DBA) substrate. DBA substrates with different metallization were thermally cycled between -55 oC and 250 oC. Unlike with the DBC substrate, no delamination of aluminum from the aluminum nitride ceramic base-plate was observed for the DBA substrates. However, aluminum surface became roughened during the thermal cycling test. It was believed that in the high-temperature regime, the significant amount of thermomechanical stress and grain-scale deformation would cause recrystallization and grain-boundary sliding in the aluminum layer, which would further lead to the observed increase in surface roughness. The influence of metallization over the aluminum surface on the extent of surface roughness was also characterized. In addition to evaluating the reliability of nanoscale silver paste and DBA substrate individually, this work also conducted experiments that characterize the compatibility of nanoscale silver paste on DBA substrate in terms of reliability in a high-temperature environment. In the large-area attachment, the sintered silver was found to be very compliant with the deformed aluminum. The device-to-silver and silver-to-substrate interfaces remain intact after up to 800 cycles. No large scale delamination and horizontal cracks were observed. However, some vertical crack lines began to show after certain number of cycles. It was believed that these vertical cracks were caused by the thermomechanical stresses in the sintered silver layer. In addition, with regard to the thermal performance, since most of the heat was generated from the semiconductor devices and were transferred vertically through the die-attach material to substrate, these vertical cracks were also considered more advantageous than horizontal cracks. / Ph. D.