Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. In this dissertation, thermal stresses and interfacial reliability of TSV structures are analyzed by combining analytical and numerical models with experimental measurements. First, three-dimensional near-surface stress distribution is analyzed for a simplified TSV structure consisting of a single via embedded in a silicon (Si) wafer. A semi-analytic solution is developed and compared with finite element analysis (FEA). For further study, the effects of anisotropic elasticity in Si and metal plasticity in the via on the stress distribution and deformation are investigated. Next, by micro-Raman spectroscopy and bending beam technique, experimental measurements of the thermal stresses in TSV structures are conducted. The micro-Raman measurements characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the bending beam technique measures the average stress and viii deformation in the TSV structures. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias is analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. To study the impacts of the thermal stresses on interfacial reliability of TSV structures, an analytical solution is developed for the steady-state energy release rate as the upper bound of the driving force for interfacial delamination. The effect of crack length and wafer thickness on the energy release rate is studied by FEA. Furthermore, to model interfacial crack nucleation, an analytical approach is developed by combining a shear lag model with a cohesive interface model. Finally, the effects of structural designs and the variation of the constituent materials on TSV reliability are investigated. The steady state solutions for the energy release rate are developed for various TSV designs and via materials (Al, Cu, Ni, and W) to evaluate the interfacial reliability. The parameters for TSV design optimization are discussed from the perspectives of interfacial reliability. / text

This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays. / text