Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells. / AFRIKAANSE OPSOMMING: "Rapid Single Flux Quantum" (RSFQ) selle is van sleutelbelang in die ontwerp van komplekse en toepaslike RSFQ elektroniese stroombane. Hierdie selle is laevlak stroombaanelemente wat herhaaldelik gebruik word om groter RSFQ bane mee te bou. Versigtige ontwikkeling is nodig om hierdie selle eenvoudig vir uitleg en vervaardiging te hou terwyl dit ook betroubaar is vir wye gebruik. Selfunksionaliteit word geverifieer deur middel van simulasies, waarna selle vir vervaardiging uitgelê word in spesiale sagtewarepakette. Induktansie van supergeleierstrukture op vervaardigde skyfies word deur versigtige modellering met behulp van numeriese veldoplossingsagteware onttrek. In hierdie tesis is ’n selbiblioteek ontwerp deur bestaande (gepubliseerde) selle verder te analiseer en optimeer, en deur nuwe selle te ontwerp om die biblioteek volledig te maak. Selle wat aangepas is vir hierdie biblioteek sluit die Josephson-Transmissielyn (JTL), Verdeler, Samevoeger, DWipkring (DFF), T-Wipkring (TFF), NIE, EN, OF en XOF, asook die DC-SFQ en SFQ-DC selle en Passiewe Transmissielyn (PTL) drywers en ontvangers in. Nuwe selle sluit die NOF, NEN en XNOF hekke in. Die selle is ontwerp en uitgelˆe vir beide IPHT se RSFQ1D 1kA/cmª en Hypres se4.5kA/cmª prosesse. Die selle in die biblioteek toon goeie voorspanningstroom-werksmarges, soos verkry deur simulasie (> ±26%). Parameters en berekende induktansies vir alle selle word in die tesis gelys vir naslaandoeleindes. Vir die daarstel van ’n volledige en geverifieerde RSFQ selbiblioteek is selontwerpe vir vervaardiging na IPHT en Hypres gestuur. Aangesien vervaardiging slegs een maal per jaar by IPHT gedoen word, is die skyfies egter nog nie beskikbaar nie. Na vervaardiging kan die skyfies egter getoets word om selfunksionaliteit in die laboratorium te meet. Ten einde hierdie toetsing vir enige medewerker te vergemaklik, word alle toetsparameters soos voorspanningstroom en intreeseinpatrone in die tesis gedefinieer.

Thesis (MScEng)--Stellenbosch University, 2011. / ENGLISH ABSTRACT: An investigation of the functional similarities and di erences between a combline lter and an evanescent-mode waveguide lter is presented. The design theory of the two types of lters is outlined. Two lters are designed to operate at a centre frequency of 2 GHz with a 5% bandwidth using similar waveguide dimensions, but using the two di erent design theories. The bandpass characteristics of the two lters are then compared over the primary passband and over a broad range of frequencies to observe the stopband characteristics. It is shown that a combline lter with a large groundplane spacing behaves like an evanescent-mode waveguide lter but a di erence in bandwidth exists between the two. Di erent aspects related to the manufacture of coaxial cavity lters are addressed with speci c emphasis on cost reduction. The considerations to be made when choosing the right materials, manufacturing techniques and surface nishes for microwave coaxial cavity lters so that good performance is obtained while reducing the overall costs associated with manufacturing are discussed. The concept of Design for Manufacture (DFM) is discussed. Three combline lters are designed for reduced manufacturing cost, applying di erent changes in the physical structure to suit the speci c manufacturing technique used. Two of these have the same design speci cations, operating at a centre frequency of 1.3 GHz with a 10% bandwidth but are designed for manufacture using two di erent manufacturing techniques: milling and wire-cutting EDM. The third lter is designed for manufacture using a combination of the milling and wirecutting processes to have a bandwidth of 1.8% with the primary passband centred at 2.125 GHz. Problems encountered in manufacturing are explained, one of which results in the use of waterjet cutting for the manufacture of lters initially supposed to be manufactured using wirecutting EDM. Measurement results for the manufactured lters show a good agreement between the bandwidths of the 3D electomagnetic simulation results. The obtained results also show the e ects of poor surface nishing and of deformations on the resonant frequency and the unloaded Q of the lters. / AFRIKAANSE OPSOMMING: 'n Studie van die funksionele ooreenkomste en verskille tussen kamlyn lters en gol eier-onder-afknip lters word aangebied. Die ontwerpstegnieke van beide tipes lters word aangebied. Twee lters word ontwerp met 'n senterfrekwensie van 2GHz en 'n bandwydte van 5%, met soortgelyke gol eierafmetings maar deur gebruik te maak van die verskillende ontwerpstegnieke. Die gedrag van die twee lters word vergelyk in die deurlaatband sowel as oor 'n wye stopband. Dit word getoon dat 'n kamlyn lter met 'n groot grondvlakspasi ering soos 'n gol eier-onder-afknip lter optree, met 'n verskil in bandwydte. Verskillende aspekte wat verband hou met die vervaardiging van koaksiale lters, met spesi eke klem op koste vermindering, word aangebied. Die oorwegings wat die keuses van materiaal, vervaardigingstegnieke en oppervlakte afwerking be nvloed word bespreek. Die konsep van Ontwerp vir Vervaardiging (DFM in Engels) word bespreek. Drie kamlyn lters word ontwerp vir verminderde vervaardigingskoste deur die siese sruktuur aan te pas by die spesi eke vervaardigingstegniek. Twee van die lters het dieselfde spesi kasie, naamlik 'n senterfrekwensie van 1.3GHz en 'n 10% bandwydte, maar word ontwerp vir twee verskillende vervaardigingsprosesse, naamlik frees en draadsny. 'n Derde lter word ontwerp vir 'n kombinasie van hierdie twee prosesse, en met 'n senterfrekwensie van 2.125GHz en 'n bandwydte van 1.8%. Probleme met die vervaardiging word bespreek, onder andere die verandering van draadsny na water-sny tegnieke. Gemete resultate toon goeie ooreenstemming met die teoretiese analise wat die bandwydtes betref, maar swak oppervlak afwerking het 'n verswakking van die onbelaste Q van die resoneerders tot gevolg.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / A process was developed to design and manufacture a dc SQUID magnetometer. Superconductor theory is given as a foundation to explain the Josephson junction. This knowledge is applied to explain the ideal and practical dc SQUID. The design of the dc SQUID is done with inductance calculation formulas. Each step of the manufacturing process is discussed in detail. Many improvements have been made to the process to make each step reproducible. The steps in the manufacturing process that were done in-house are: manufacturing an YBa2Cu3O7−d pellet, depositing the thin film with the pulsed laser deposition process, creating a mask with the UV lithography process, wet etching the circuit and depositing silver contact pads with thermal evaporation. The device is packaged on a printed circuit board device holder and shielded with a mu-metal shield. A test setup is developed to test the final device. Each step in the manufacturing process was successful. The final device did not work, due to oxidisation of the YBa2Cu3O7−d thin film.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The use of older and slower protocols has become increasingly difficult to justify due to the rapid pace at which telecommunications are advancing. To keep up to date with the latest technologies, the communications system must be designed to accommodate the transparent insertion of new communications standards in all the stages of a system. The system should, however, also remain compatible with the older standards so as not to demand an upgrade of the older systems. The concept of a software defined radio was introduced to overcome these problems. In a software defined radio system, the functionality of the communications system is defined in software, which removes the the need for alterations to the hardware during technology upgrade. To maintain interoperatibilty, the system must be based on a standardised architecture. This would further allow for enhanced scalability and provide a plug-andplay feature for the components of the system. In this thesis, generic signal processing software components are developed to illustrate the creation of a basic software modem that can be parameterised to comply fully, or partially, to various standards.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / In this thesis we present a human-computer interface (HCI) system for disabled persons using only a basic web camera. Mouse movements are simulated by small movements of the head, while clicks are simulated by eye blinks. In this study, a system capable of face tracking, eye detection (including iris detection), blink detection and finally skin detection and face recognition has been developed. A detection method based on Haar-like features are used to detect the face and eyes. Once the eyes have been detected, a support vector machines classifier is used to detect whether the eye is open or closed (for use in blink detection). Skin detection is done using K-means clustering, while Eigenfaces is used for face recognition. It is concluded that using a web camera as a human-computer interface can be a viable input method for the severely disabled.

Thesis (MScEng)--Stellenbosch University, 2012 / ENGLISH ABSTRACT: Modern-day online applications are required to deal with an ever-increasing number of users without decreasing in performance. This implies that the applications should be scalable. Applications hosted on static servers are in exible in terms of scalability. Cloud computing is an alternative to the traditional paradigm of static application hosting and o ers an illusion of in nite compute and storage resources. It is a way of computing whereby computing resources are provided by a large pool of virtualised servers hosted on the Internet. By virtually removing scalability, infrastructure and installation constraints, cloud computing provides a very attractive platform for hosting online applications. This thesis compares the cloud computing infrastructures Google App Engine and AmazonWeb Services for hosting web applications and assesses their scalability performance compared to traditionally hosted servers. After the comparison of the three application hosting solutions, a proof-of-concept software framework for the provisioning and deployment of automatically scaling applications is built on Amazon Web Services which is shown to be best suited for the development of such a framework.

Thesis (MScEng)--Stellenbosch University, 2012. / ENGLISH ABSTRACT: This research combines symbolic execution, a formal method of static analysis, with various test adequacy criteria, to explore the e ectiveness of using symbolic execution for calculating code coverage on a program's existing JUnit test suites. Code coverage is measured with a number of test adequacy criteria, including statement coverage, branch coverage, condition coverage, method coverage, class coverage, and loop coverage. The results of the code coverage calculation is then used to automatically generate JUnit test cases for areas of a program that are not su ciently covered. The level of redundancy of each test case is also calculated during coverage calculation, thereby identifying fully redundant, and partially redundant, test cases. The combination of symbolic execution and code coverage calculation is extended to perform coverage calculation during a manual execution of a program, allowing testers to measure the e ectiveness of manual testing. This is implemented as an Eclipse plug-in, named ATCO, which attempts to take advantage of the Eclipse workspace and extensible user interface environment to improve usability of the tool by minimizing the user interaction required to use the tool. The code coverage calculation process uses constraint solving to determine method parameter values to reach speci c areas in the program. Constraint solving is an expensive computation, so the tool was parallellised using Java's Concurrency package, to reduce the overall execution time of the tool. / AFRIKAANSE OPSOMMING: Hierdie navorsing kombineer simboliese uitvoering, 'n formele metode van statiese analise, met verskeie toets genoegsaamheid kriteria, om die e ektiwiteit van die gebruik van simboliese uitvoer te ondersoek vir die berekening van kode dekking op 'n program se bestaande JUnit toets stelle. Kode dekking word gemeet deur verskeie toets genoegsaamheid kriteria, insluited stelling dekking, tak dekking, kondisie dekking, metode dekking, klas dekking, en lus dekking. Die resultate van die kode dekking berekeninge word dan gebruik om outomaties JUnit toets voorbeelde te genereer vir areas van 'n program wat nie doeltre end ondersoek word nie. Die vlak van oortolligheid van elke toets voorbeeld word ook bereken gedurende die dekkingsberekening, en daardeur word volledig oortollige, en gedeeltelik oortollige, toets voorbeelde identi seer. Die kombinasie van simboliese uitvoer en kode dekking berekening is uitgebrei deur die uitvoer van dekking berekeninge van 'n gebruiker-beheerde uitvoer, om sodoende kode dekking van 'n gebruiker-beheerde uitvoer van 'n program te meet. Dit laat toetsers toe om die e ektiwiteit van hulle beheerde uitvoer te meet. Bogenoemde word ge mplimenteer as 'n Eclipse aanvoegsel, genaamd ATCO, wat poog om voordeel te trek vanuit die Eclipse werkspasie, en die uitbreibare gebruiker oordrag omgewing, om die bruikbaarheid van ATCO te verbeter, deur die vermindering van die gebruiker interaksie wat benodig word om ATCO te gebruik. Die kode dekking berekeningsproses gebruik beperking oplossing om metode invoer waardes te bereken, om spesi eke areas in die program te bereik. Beperking oplossing is 'n duur berekening, so ATCO is geparalleliseer, met behulp van Java se Concurrency pakket, om die algehele uitvoer tyd van die program te verminder.

Thesis (MScEng)--Stellenbosch University, 2012 / ENGLISH ABSTRACT: The class-D audio power amplifier has found widespread use in both the consumer and professional audio industry for one reason: efficiency. A higher efficiency leads to a smaller and cheaper design, and in the case of mobile devices, a longer battery life. Unfortunately, the basic class-D amplifier has some serious drawbacks. These include high distortion levels, a load dependent frequency response and the potential to radiate EMI. Except for EMI, the aforementioned issues can be mitigated by the proper implementation of global negative feedback. Negative feedback also has the potential to indirectly reduce EMI, since the timing requirements of the output devices can be relaxed. This thesis discusses the design of a clocked analogue controlled pulse-width modulated class-D audio amplifier with global negative feedback. The analogue control loop is converted to the z-domain by modelling the PWM comparator as a sampling operation. A method is implemented that improves clip recovery and ensures stability during over-modulation. Loop gain is shaped to provide a high gain across the audio band, and ripple compensation is implemented to minimize the negative effect of ripple feedback. Experimental results are presented. / AFRIKAANSE OPSOMMING: Die klas-D klankversterker geniet wydverspreide gebruik in beide die verbruiker en professionele oudio industrie vir een rede: benuttingsgraad. ’n Hoër benuttingsgraad lei tot ’n kleiner en goedkoper ontwerp, en in die geval van draagbare toestelle, tot langer batterylewe. Ongelukkig het die basiese klas-D klankversterker ernstige tekortkominge, naamlik hoë distorsievlakke, ’n lasafhanklike frekwensierespons en die vermoë om EMI te genereer. Behalwe vir EMI kan hierdie kwessies deur die korrekte toepassing van globale negatiewe terugvoer aangespreek word. Negatiewe terugvoer het ook die potensiaal om EMI indirek te verminder, aangesien die tydvereistes van die skakel stadium verlaag kan word. Hierdie tesis bespreek die ontwerp van ’n geklokte analoog-beheerde pulswydte-modulerende klas-D klankversterker met globale negatiewe terugvoer. Die analoogbeheerlus word omgeskakel na die z-vlak deur die PWM vlakvergelyker as ’n monster operasie te modelleer. ’n Metode word geïmplementeer wat die stabiliteit van die lus verseker tydens oormodulasie. Die lusaanwins word gevorm om ’n hoë aanwins in die oudioband te verseker en riffelkompensasie word geïmplementeer om die negatiewe effek van terugvoerriffel teen te werk. Eksperimentele resultate word voorgelê.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / This thesis describes the design of a high performance, floating-point, standalone embedded system that is appropriate for speech and audio processing purposes. The system successfully employs the Analog Devices TigerSHARC TS201 600MHz floating point digital signal processor as a CPU, and includes 512MB RAM, a Compact Flash storage card interface as non-volatile memory, a multi-channel audio input and output system with two programmable microphone preamplifiers offering up to 65dB gain, a USB interface, a LCD display and a push-button user interface. An Altera Cyclone II FPGA is used to interface the CPU with the various peripheral components. The FIFO buffers within the FPGA allow bulk DMA transfers of audio data for minimal processor delays. Similar approaches are taken for communication with the USB interface, the Compact Flash storage card and the LCD display. A logic analyzer interface allows system debugging via the FPGA. This interface can also in future be used to interface to additional components. The power distribution required a total of 11 different supplies to be provided with a total consumption of 16.8W. A 6 layer PCB incorporating 4 signal layers, a power plane and ground plane was designed for the final prototype. All system components were verified to be operating correctly by means of appropriate testing software, and the computational performance was measured by repeated calculation of a multi-dimensional Gaussian log-probability and found to be comparable with an Intel 1.8GHz Core2Duo processor. The design can therefore be considered a success, and the prototype is ready for development of suitable speech or audio processing software.