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The purpose of this research and the corresponding project is to explore and interpret the qualities of the traditional art form of Indian miniature paintings into a digital, time based medium. These are beautiful, finely-drawn paintings with rich detailed patterns and striking bold colors. Intricately and meticulously drawn, they employ an alternative means of representation distinctly different from a conventional lens-based perspective. Most 3-dimensional digital media makes use of either a real or a virtual camera to inform the representation of space. In this project I deviate from this convention to create a new visual style for animation. The project demonstrates how a consistent yet different visual look can be achieved that retains the richness and visual expression of the traditional painting style through the use of new technology.

This dissertation presents a novel [delta sigma] analog-to-digital converter architecture which replaces the operational amplifier-based integrator with a pair of tunable oscillators. A switched-capacitor V-I converter is used to combine the input voltage with a feedback DAC output and convert it into a current for two pseudo-differential current-controlled oscillators. The oscillator outputs are counted with a digital counter, and a digital back-end [delta sigma] modulator is used to truncate the high-resolution counter outputs for the feedback DAC path. This architecture has compelling advantages in deep sub-micron and emerging technologies where supply voltages are decreasing to a point that traditional analog architectures are no longer feasible. Additionally, this architecture takes advantage of the increased speed in these short-channel technologies. Measured results on a 6.08mW prototype in TSMC 0.18um achieving 63.5dB in a 2MHz bandwidth are presented. / text

There is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored. First, I propose a mostly-digital time-based oversampling delta-sigma (∆Σ) ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects. In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) processes. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and ∼50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm² , while the second generation ADC core occupies 0.0192 mm² . The two prototypes can be categorized as some of the smallestarea modulators in the literature. Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored over traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area. / text

Time-based prospective memory has been found to be negatively affected by aging, possibly as a result of the declining frontal function that often accompanies aging. In the present study we investigated the role of the frontal lobes in prospective memory. Based upon their scores on a composite measure of frontal function, 32 older adults were characterized as possessing high- or low-frontal function, and were then tested on a time-based laboratory prospective memory task. Overall age effects were also assessed and each of the frontal groups was compared to a group of 32 younger adults. High-frontal functioning participants demonstrated better prospective memory than low-frontal functioning participants, and were not distinguishable from younger adults. The results of this study suggest that it is not aging per se that disrupts prospective memory performance, but it is instead the diminished frontal function seen in a subset of older adults.

Prospective memory is colloquially known as “remembering to remember” and refers to forming an intention in the present time to fulfill at some point in the future. It has previously been studied within the context of executive functioning (i.e., purposive and goal directed behavior) and impulsive behaviors (e.g., gambling, risk seeking) within clinical populations. This study sought to further elucidate the relationships of impulsivity and executive functions on prospective memory in a non-clinical population. One hundred and nine undergraduates completed the UPPS-P impulsivity self-report questionnaire, three cognitive tasks measuring components of executive function, (i.e., planning, inhibition, and switching), and a Complex Prospective Memory Task that included Time- and Event-based cues. The UPPS-P and executive function tasks did not significantly predict the Complex Prospective Memory Task. However, executive function was found to be a significant predictor above and beyond that of impulsivity for a component of the Time-based prospective memory task. Implications of the results and future directions are discussed.

This research will focus on how applied the Time-based process mapping applied into the practical case. By comparing the difference between traditional process mapping tools and Time-based process map(TBPM), this research find out which kind of company and situation is suitable for TBPM and the reasons why the TBPM is suitable for this situation. The major research happens at IKEA’s DC terminal in Torsvik, Jönköping, Sweden. The holistic process will be mentioned in the beginning of the research, in order to better understand the current state in IKEA’s distribution centrel.

Distributed real-time applications require support from the underlying middleware to meet the strict requirements for jitter, latency, and bandwidth. While most existing middleware standards such as MPI do not support Quality of Service (QoS), the MPI/RT standard supports QoS in addition to striving for high performance. This thesis presents HARE, the first known implementation of a subset of the MPI/RT 1.1 standard with time-driven QoS support. This thesis proves the following hypothesis: It is possible to achieve zero-sided communication (a model of communication characterized by the absence of any explicit per-message transfer calls by any of the participating sides) in a real-time environment using a QoS contract between an application and message-passing middleware. Furthermore, it is shown that the performance and predictability of a time-driven task using zero-sided communication is better than that of a best-effort task. The hypothesis is validated through compact MPI/RT application programs that achieve zero-sided communication.