This study aims to find an effective linear combination of factors in different economic cycle periods and then construct two factor timing multi-factor alpha models, one each for the expansion and contraction periods. Then, we wish to examine a further two effects, namely calendar effect and cross effect. The calendar periods are divided into the first half year and the second half year. The cross effect is the combination of the economic cycle and the calendar effect. In addition, this study puts different loadings in core and satellite descriptors, which means we wish to examine which descriptors are more important when we rebalance our portfolio weekly. The empirical results show that the Value factor is effective in expansion and the first half year, and the Size and Earnings Quality factors are effective in contraction and the second half year. Moreover, the Price Momentum and Trading Activity factors are effective most of the time. We find that the optimal weight for core descriptors is 0.3 and for satellite descriptors is 0.7. Finally, the information ratios of our models are superior to the Standard alpha model by Hsu et al. (2011) and the Market Trend-based alpha model by Wang (2011). Taking the AMCross as an example, when the tracking error is below 3%, the IR is 1.40, the active return is 3.09%, the tracking error is 2.20%, the turnover rate is 207% and the transaction costs are 1.2%.

As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology. In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated. Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

In recent times, there has been an increased focus on the problem of information exchange between two nodes using a relay node. The introduction of physical layer network coding has improved the throughput efficiency of such an exchange. In practice, the reliability of information exchange using this scheme is reduced due to synchronization issues at the relay node. In this thesis, we deal with timing synchronization of the signals received at the relay node. The timing offsets of the signals received at the relay node are computed based on the propagation delays in the transmitted signals. However, due to the random attenuation of signals in a fading channel, the near far problem is inherent in this situation. Hence, we aim to design near far resistant delay estimators for this system. We put forth four algorithms in this regard. In all the algorithms, propagation delay of each signal is estimated using a known preamble sent by the respective node at the beginning of the data packet. In the first algorithm, we carefully construct the preamble of each data packet and apply the MUSIC algorithm to overcome the near far problem. The eigenstructure of the correlation matrix is exploited to estimate propagation delay. Secondly, the idea of interference cancellation is implemented to remove the near far problem and delay is estimated using a correlator. Thirdly, a modified decorrelating technique is presented to negate the near far problem. Using this technique we aim to obtain an estimate of the weak user's delay that is more robust to errors in the strong user's delay estimate. In the last algorithm, pilot signals with desired autocorrelation and cross correlation functions are designed and a sliding correlator is used to estimate delay. Even though this approach is not near far resistant, performance results demonstrate that for the length's of preamble considered, this algorithm performs similar to the other algorithms.

Abstract The research is to discover the competition among banks with platinum card without yearly charge. First of all, the general situation of the market of platinum card from May 2002 to June 2003 will be analyzed. Second, it is for the purpose of discovering the strategic groups, dynamic resource analysis, and reaction time of competitors respectively of the whole market of platinum card. Some factors that can influence the strategy of banks, such as time, competition, customers, resources and other parties will be regarded as analytic aspects. Finally, new 7¡¦S model will be used as an analytic tool in order to understand the main competitive strategies of China Trust Bank, Taishin Bank and Fubon Bank, which are the three primary competitors in the market. In this research, the primary information is attempted to be collected via deep interview in qualitative research method; then, the analysis will be completed by means of the integration of secondary information. The results of the research are also divided into five parts: 1. The interaction between banks and timing: Banks of small scale will prefer to follow up after the market leader joins; the timing that the competition launches the product will affect the policy of banks, and they will adjust the major functions or services of the products according to the different timing of entrance. 2. The interaction between banks and competition: Thorough differentiating the main competitors of banks, they can arrange the order and priority of the actions while implementing the strategies. In the future, banks should start to think from ¡§how to increase competitors¡¦ movable obstacle¡¨, and demolish the features that strategies are highly similar and easy to be imitated in the credit card industry. 3. The interaction between banks and customers: Banks must understand the difference of needs between what customers recognize and what banks recognize; then, endeavor to minimize this difference. Banks should undertake how to raise customers¡¦ switch cost, to find their needs that they themselves do not discover yet, and try to increase their loyalty. 4. The interaction between banks and resources: Banks should consider from a long-term point of view for the accumulation and creation of their internal resources, and the application for the resources lever. In addition, resources and capabilities required for the future should be trained up in advance. On the other hand, the obtainment of external resources is as important as the training of internal resources; hence, banks should think both of them highly and take advantage of each other. 5. The interaction between banks and other parties: The future competition might be the competition between industry networks, financial control companies, blocs or issuing organizations. Banks should improve their competency and increase the bargaining power with their partners. Therefore, they are able to look for a good partner and raise the barrier of exit of partners. Last but not least, some specific suggestions would be addressed to the banks of big, middle and small scales for the reference of their strategic planning in the future. Keyword: platinum card, competitive strategy, timing, and resource capability.

Abstract This research is based on the Taiwan Stock Index. We can use the technical analysis of K-line which may reveal the signal of buying or selling in actual operation. It can help the investors to deciside the timing to buy or sell. The above method is a kind of stock index in actual testing analysis during the period from 1993 to 2002. The conclusions of our research are the following: 1. The signal of buying or selling can create good return according to the theory of K-line during the research period and it sometimes can offers higher return than the interest rate offered by the bank. It is a reliable method for most of the investors. 2. The signal of up or down can't be judged according to the theory of K-line during the period of stagnancy. We must judge the market and predict the future after the ending of stagnancy of K-line in order to obtain the best point of buying or selling.

Due to the uncertainties introduced by the propagation channel, and RF and mixed signal circuits imperfections, digital communication receivers require efficient and robust signal acquisition algorithms for timing and carrier recovery, and interfer- ence rejection. The main theme of this work is the development of efficient and robust signal synchronization and interference rejection schemes for narrowband, wideband and ultra wideband communications systems. A series of novel signal acquisition schemes together with their performance analysis and comparisons with existing state-of-the- art results are introduced. The design effort is first focused on narrowband systems, and then on wideband and ultra wideband systems. For single carrier modulated narrowband systems, it is found that conventional timing recovery schemes present low efficiency, e.g., certain feedback timing recov- ery schemes exhibit the so-called hang-up phenomenon, while another class of blind feedforward timing recovery schemes presents large self-noise. Based on a general re- search framework, we propose new anti-hangup algorithms and prefiltering techniques to speed up the feedback timing recovery and reduce the self-noise of feedforward tim- ing estimators, respectively. Orthogonal frequency division multiplexing (OFDM) technique is well suited for wideband wireless systems. However, OFDM receivers require high performance car-rier and timing synchronization. A new coarse synchronization scheme is proposed for efficient carrier frequency offset and timing acquisition. Also, a novel highly accurate decision-directed algorithm is proposed to track and compensate the residual phase and timing errors after the coarse synchronization step. Both theoretical analysis and computer simulations indicate that the proposed algorithms greatly improve the performance of OFDM receivers. The results of an in-depth study show that a narrowband interference (NBI) could cause serious performance loss in multiband OFDMbased ultra-wideband (UWB) sys- tems. A novel NBI mitigation scheme, based on a digital NBI detector and adaptive analog notch filter bank, is proposed to reduce the effects of NBI in UWB systems. Simulation results show that the proposed NBI mitigation scheme improves signifi- cantly the performance of a standard UWB receiver (this improvement manifests as a signal-to-noise ratio (SNR) gain of 9 dB).

Modern digital designs require high performance and low cost. In this scenario, timing analysis is an essential step for each phase of the integrated circuit design cycle. To minimize the design turn-around time, the ability to correctly predict the timing behavior of the chip is extremely important. This has resulted in a demand for techniques to perform an accurate timing analysis. A number of existing timing analysis approaches are available. Most of these are pessimistic in nature due because of some inherent inaccuracies in the modeling of the timing behavior of logic gates. Although some techniques use accurate gate delay models, they have only been used to calculate the longest sensitizable delay or the shortest topological path delay for the circuit. In this work, a procedure to and the shortest destabilizing delay, as well as the longest sensitizable delay of a static CMOS circuit is developed. This procedure is also able to determine the exact circuit path as well as the input vector transition for which the shortest destabilizing (or longest sensitizable) delay can be achieved. Over a number of examples, on an average, the minimum destabilizing delay results in an improvement of 24% as compared to the minimum static timing analysis approach. The maximum sensitizable timing analysis results in an improvement of 7% over sensitizable timing analysis with pin-to-output delays. Therefore, the results show that the pessismism in timing analysis can be considerably decreased by using data dependent gate delays for maximum as well as minimum sensitizable timing analysis.

The recent pollution norms have brought a strong emphasis on the reduction of diesel engine emissions. Low temperature combustion technology such as premixed compression ignition (PCI) has the capability to significantly and simultaneously reduce nitric oxides (NOx) and particulate matter (PM), thus meeting these specific pollution norms. There has been, however, observed loss in fuel conversion efficiency in some cases. This study analyzes how energy transfer and brake fuel conversion efficiency alter with (or are affected by) injection timings and exhaust gas recirculation (EGR) rate. The study is conducted for PCI combustion for four injection timings of 9°, 12°, 15° and 18° before top dead center (BTDC) and for four exhaust gas recirculation (EGR) rates of 39%, 40%, 41% and 42%. The data is collected from the experimental apparatus located in General Motors Collaborative Research Laboratory at the University of Michigan. The heat release is calculated to obtain various in-cylinder energy transfers. The brake fuel conversion efficiency decreases with an increase in EGR. The decrease in the brake fuel conversion efficiency is due to the decrease in work output. This decrease is due to an increase in the pumping work and an increase in friction and decrease in gross indicated work. The decrease in the combustion efficiency is because of the increased formation of unburnt products due to increased ignition delay caused by the application of EGR and decreasing air-fuel (A/F) ratio. A definite trend is not obtained for the contribution of heat transfer to the total energy distribution. However the total heat transfer decreases with retardation of injection timing because of decreasing combustion temperature. As the injection timing is retarded, the brake fuel conversion efficiency is found to decrease. This decrease is because of a decrease in net work output. This is because the time available for utilization of the energy released is less because of late combustion. The total heat transfer decreases with retardation of injection timing because of decreasing combustion temperature. The contribution of heat transfer to the total energy distribution decreases with increase in EGR.

Timing analysis is a key sign-off step in the design of today's chips, but technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models ranging from the basic MOSFET device model to full-chip models of important performance metrics including power, frequency of operation, etc. The assessment of the quality of such models is an important activity, but it is becoming harder and more complex with rising levels of variability and the increase in the number of systematic effects observed in modern CMOS processes. The purpose of this research is (i) to introduce special-purpose test structures that specifically focus on ensuring the accuracy of gate timing models, and (ii) to introduce methods that analyze the extracted information, in the form of path delay measurements, using the proposed test structures. The certification of digital design correctness (the so-called signoff) is based largely on the results of performing Static Timing Analysis (STA), which, in turn, is based entirely on the gate timing models. The proposed test structures compare favorably to alternative approaches; they are far easier to measure than direct delay measurement, and they are much more general than simple ring-oscillator structures. Furthermore, the structures are specified at a high level, allowing them to be synthesized using a standard ASIC place-and-route flow, thus capturing the local layout systematic effects which can sometimes be lost by simpler (e.g., ring oscillator) structures. For the silicon timing analysis, we propose methods that deduce segment delays from the path delay measurements. These estimated segment delays using our methods can be directly compared with the timing models. Therefore, it will be easy to identify the cause of timing mismatches. Deducing segment delays from path delays, however, is not an easy problem. The difficulties associated with deconvolving segment delays from measured path delays come from insufficient sampling points. To overcome this limitation, we first group the segments based on certain characteristics of segments, and adapt Moore-Penrose pseudo-inverse method to approximately solve the segment delays. Secondly, we used equality-constrained least squares methods, which enable us to find a unique and optimized solution of segment delays from underdetermined systems. We also propose another improved test structure that has a built-in test pattern generator, and hence does not require ATPG (Automatic Test Pattern Generation). It is a self-timed circuit, and this feature makes the test structure run as fast as it can. Therefore, measurements can be made under high speed switching conditions. Finally, we can study dynamic effects such as timing effects of different levels of switching activities and voltage drop with the new test structure. / text

ITC/USA 2013 Conference Proceedings / The Forty-Ninth Annual International Telemetering Conference and Technical Exhibition / October 21-24, 2013 / Bally's Hotel & Convention Center, Las Vegas, NV / Telemetry ground stations spread over geographically diverse areas are well suited for use in passively locating the source of a distant transmitted signal. In a favorable positioning of receive sites, the accuracy of these passive localization techniques can compete with the accuracy of radars. In these cases, use of receive only assets is a less expensive alternative than the use of a radar's scarce resources. Until recently, the major technical challenge to implementation of the passive localization techniques of time-difference of arrival (TDOA) and frequency-difference of arrival (FDOA) has been the frequency and time stability of geographically separated receivers. Advances in GPS based timing and frequency references has made the implementation of TDOA and FDOA feasible. This paper shows how these limitations have been overcome using the current telemetry assets at the Reagan Test Site in Kwajalein Atoll.