Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / Bibliography: leaf 44. / by Nathan Graham. / B.S.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / Bibliography: leaves 141-142. / by David Adams Garlow. / M.S.

As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced. This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is not as sensitive to variability as synchronous, while fault tolerance allows continued functional operation in the presence of defects. GasP is a self-timed asynchronous design that provides high performance in a simple circuit. Quadded Logic, is a gate level fault tolerant methodology. This study presents Quadded GasP, a fault tolerant asynchronous design. This work demonstrates that Quadded GasP circuits continue to function within performance expectations when faults are present. The increased area and reduced performance costs of Quadded GasP area also evaluated. These results show Quadded GasP circuits are a viable option for managing process variation and defects. Application of these circuits will provide decreased development and test times, as well as increased yield.

Thesis (M.S.)--Brigham Young University, Department of Mechanical Engineering, 2004. / Includes bibliographical references (p. 259-261).

Microelectronic systems packaging involves layout dimensions of the order of microns. During manufacturing, process variations will cause parameters to deviate from their nominal values. As a result, the manufactured circuit may no longer meet the specifications it is designed to satisfy. When producing high volume of electronics, assembly yield becomes very important. This is where tolerance margins of the design parameters play an important role. This means that the performance specifications should be satisfied if the process variations are within the given tolerance margin of design parameters. Research has been done on circuit level design for manufacturability methods. The main objective of the research is to study the layout level DFM methods for signal integrity issues and embedded Rf passive components and use design centering methodology to improve the output yield value. In this dissertation, emphasis is also laid on taking care of the regression error while calculating the yield value. With the developed method, the number of design iteration cycles to maximize yield is significantly reduced.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (Ph.D.)--University of Melbourne, Dept. of Civil and Environmental Engineering, 2006. / Typescript. Includes bibliographical references (leaves 223-235).

Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaves

Thesis (Ph. D.)--West Virginia University, 2004. / Title from document title page. Document formatted into pages; contains xiv, 145 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 138-145).

Thesis (Ph. D.), Memorial University of Newfoundland, 1999. / Bibliography: p. 131-137.