Systems engineering introduces the notion of top-down design, which involves viewing an entire system comprised of its components as a whole functioning unit. This requires an understanding of how those components efficiently interact, with optimization of the process emphasized rather than solely focusing on micro-level system components. The traditional approach to the systems engineering process involves requirements decomposition and flow down across a hierarchy of decision making levels, in which needs and requirements at one level are transformed into a set of system product and process descriptions for the next lower level. This top-down requirements flow approach therefore requires an iterative process between adjacent levels to verify that the design solution satisfies the requirements, with no direct flow between nonadjacent hierarchy levels. This thesis introduces a methodology that enables decision makers anywhere across a system-of-systems hierarchy to rapidly and simultaneously manipulate the design space, however complex. A hierarchical decision making process will be developed in which a system-of-systems, or multiple operationally and managerially independent systems, interact to affect a series of top level metrics. This takes the notion of top-down requirements flow one step further to allow for simultaneous bottom-up and top-down design, enabled by the use of neural network surrogate models to represent the complex design space. Using a proof-of-concept case study of employing a guided projectile for mortar interception, this process will show how the iterative steps that are usually required when dealing with flowing requirements from one level to the next lower in the systems engineering process are eliminated, allowing for direct manipulation across nonadjacent levels in the hierarchy. For this system-of-systems environment comprised of a Monte Carlo based design space exploration employing rapid neural network surrogate models, both bottom-up and top-down design analysis may be executed simultaneously. This process enables any response to be treated as an independent variable, meaning that information can flow in either direction within the hierarchy.

In dieser Präsentation wird das universelle FE-Modell eines Kegelrollenlagers vorgestellt. Mittels eines Pro/ENGINEER-Layouts, basierend auf dem Top-Down Designkonzept, kann automatisch innerhalb einer kurzen Bearbeitungszeit ein geprüftes und lauffähiges FE-Modell eines Kegelrollenlagers abgeleitet werden. Dieses Modell kann z.B. in großen Getriebemodellen eingebaut werden, um eine quasistatische Betrachtung mit korrekten Lagersteifigkeiten zu ermöglichen.

In dieser Präsentation wird das universelle FE-Modell eines Kegelrollenlagers vorgestellt. Mittels eines Pro/ENGINEER-Layouts, basierend auf dem Top-Down Designkonzept, kann automatisch innerhalb einer kurzen Bearbeitungszeit ein geprüftes und lauffähiges FE-Modell eines Kegelrollenlagers abgeleitet werden. Dieses Modell kann z.B. in großen Getriebemodellen eingebaut werden, um eine quasistatische Betrachtung mit korrekten Lagersteifigkeiten zu ermöglichen.

International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / Software development is becoming less an art form and more an engineering discipline. Methods of software development which leave as little as possible to chance are constantly being sought and documented. However, the gap between what is written and what is actually applied is usually quite wide. The only way this gap can be narrowed is through practical application of these very detailed and complex methods. Since it is unlikely that the complexity of these methods will be reduced, automation must be employed wherever possible in the software development process. This paper addresses the successful development of software for the Navy's Realtime Telemetry Processing System III (RTPS III) using practical application of existing methodology in conjunction with a Computer Aided Software Engineering (CASE) tool. Based on this experience, the conclusion presents implications affecting software development the 1990s.

Der von der Firma ibb durch Herrn Mirko Krimmel geplante Vortrag im Rahmen der Saxsim 2014, umfasst die Vorgehensweise zur Entwicklung einer Getriebebaureihe als Top-Down Design. Dabei werden die Bauteilauslegungen und Festigkeitsberechnungen mit Mathcad nach der FKM-Richtlinie 2012 vorgestellt, sowie die Möglichkeit gezeigt, Mathcad als übergreifendes Steuerelement für das Skelettmodell nutzen zu können. Weitere Punkte des Vortrags behandeln die Auslegung und Simulation des Gehäuses und der Gesamtbaugruppe mit Creo Simulate 2.0. Anhand der Überprüfung des Verdrehwinkels an der Abtriebsseite infolge von elastischer Verformung der einzelnen Bauteile, zeigen die Stärken des Programms. Eine parallel zur Entwicklung laufende Simulation mit MDX bestätigte die in Mathcad errechneten Werte und lieferte so gleichzeitig eine Verifizierung der 3D-Daten. Referierende Person ist Herr Mirko Krimmel (interne Konstruktion in Petersberg).

<p>High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.</p><p>To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.</p><p>The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.</p><p>The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.</p><p>A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.</p> / Report code: LiU-Tek-Lic-2005:68.

Der von der Firma ibb durch Herrn Mirko Krimmel geplante Vortrag im Rahmen der Saxsim 2014, umfasst die Vorgehensweise zur Entwicklung einer Getriebebaureihe als Top-Down Design. Dabei werden die Bauteilauslegungen und Festigkeitsberechnungen mit Mathcad nach der FKM-Richtlinie 2012 vorgestellt, sowie die Möglichkeit gezeigt, Mathcad als übergreifendes Steuerelement für das Skelettmodell nutzen zu können. Weitere Punkte des Vortrags behandeln die Auslegung und Simulation des Gehäuses und der Gesamtbaugruppe mit Creo Simulate 2.0. Anhand der Überprüfung des Verdrehwinkels an der Abtriebsseite infolge von elastischer Verformung der einzelnen Bauteile, zeigen die Stärken des Programms. Eine parallel zur Entwicklung laufende Simulation mit MDX bestätigte die in Mathcad errechneten Werte und lieferte so gleichzeitig eine Verifizierung der 3D-Daten. Referierende Person ist Herr Mirko Krimmel (interne Konstruktion in Petersberg).

High speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers. To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase. The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW. The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW. A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done. / <p>Report code: LiU-Tek-Lic-2005:68.</p>