With the advent of new applications such as Cloud Computing, Blockchain, Big Data, and Machine Learning, modern data center network (DCN) architecture has been evolving to meet numerous challenging requirements such as scalability, agility, energy efficiency, and high performance. Among the new applications ones are expediting the convergence of high-performance computing and Data Centers. This convergence has prompted research into a single, converged data center architecture that unites computing, storage, and interconnect network in a synthetic system designed to reduce the total cost of ownership and result in greater efficiency and productivity. The interconnect network is a critical aspect of Data Centers, as it sets performance bounds and determines most of the total cost of ownership. The design of an interconnect network consists of three factors: topology, routing, and congestion control, and this thesis aims to satisfy the above challenging requirements. To address the challenges noted above, the communication patterns for emerging applications are investigated, and it is shown that the dynamic and diverse traffic patterns (denoted as *-cast), especially multi-cast, in-cast, broadcast (one-to-all), and all-to-all-cast, play a significant impact in the performance of emerging applications. Inspired by hypermesh topologies, this thesis presents a novel cost-efficient topology for large-scale Data Center Networks (DCNs), which is called HyperOXN. HyperOXN takes advantage of high-radix switch components leveraging state-of-the-art colorless wavelength division multiplexing technologies, effectively supports *-cast traffic, and at the same time meets the demands for high throughput, low latency, and lossless delivery. HyperOXN provides a non-blocking interconnect network with a relatively low overhead-cost. Through theoretical analysis, this thesis studies the topological properties of the proposed HyperOXN and compares it with other different types of interconnect networks such as Fat-Tree, Flattened Butterfly, and Hypercube-like topologies. Passive optical cross-connection networks are used in the HyperOXN topology, enabling economical, power-efficient, and reliable communication within DCNs. It is shown that HyperOXN outperforms a comparable Fat-Tree topology in cost, throughput, power consumption and cabling under a variety of workload conditions. A HyperOXN network provides multiple paths between the source and its destination to obtain high bandwidth and achieve fault tolerance. Inspired by a power-of-two-choices technique, a novel stochastic global congestion-aware load balancing algorithm, which can be used to achieve relatively optimal load balances amongst multiple shared paths is designed. It also guarantees low latency for short-lived mouse flows and high throughput for long-lasting elephant flows. Furthermore, the stability of the flow-scheduling algorithm is formally proven. Experimental results show that the algorithm successfully eliminated the interactions of the elephant and mouse DC flows, and ensured high network bandwidth utilization.

L'évolution de la technologie VLSI permet aux systèmes sur puce (SoCs) d'intégrer de nombreuses fonctions hétérogènes dans une seule puce et demande, en raison de contraintes économiques, une unique mémoire externe partagée (SDRAM). Par conséquent, la conception du système de mémoire principale, et plus particulièrement l'architecture du contrôleur de mémoire, est devenu un facteur très important dans la détermination de la performance globale du système. Le choix d'un contrôleur de mémoire qui répond aux besoins de l'ensemble du système est une question complexe. Cela nécessite l'exploration de l'architecture du contrôleur de mémoire, puis la validation de chaque configuration par simulation. Bien que l'exploration de l'architecture du contrôleur de mémoire soit un facteur clé pour une conception réussite d'un système, l'état de l'art sur les contrôleurs de mémoire ne présente pas des architectures aussi flexibles que nécessaire pour cette tâche. Même si certaines d'entre elles sont configurables, l'exploration est restreinte à des ensembles limités de paramètres tels que la profondeur des tampons, la taille du bus de données, le niveau de la qualité de service et la distribution de la bande passante. Plusieurs classes de trafic coexistent dans les applications réelles, comme le trafic de service au mieux et le trafic de service garanti qui accèdent à la mémoire partagée d'une manière concurrente. En conséquence, la considération de l'interaction entre le système de mémoire et la structure d'interconnexion est devenue vitale dans les SoCs actuels. Beaucoup de réseaux sur puce (NoCs) fournissent des services aux classes de trafic pour répondre aux exigences des applications. Cependant, très peu d'études considèrent l'accès à la SDRAM avec une approche système, et prennent en compte la spécificité de l'accès à la SDRAM dans les systèmes sur puce à base de réseaux intégrés. Cette thèse aborde le sujet de l'accès à la mémoire dynamique SDRAM dans les systèmes sur puce à base de réseaux intégrés. Nous introduisons une architecture de contrôleur de mémoire totalement configurable basée sur des blocs fonctionnels configurables, et proposons un modèle de simulation associé relativement précis temporellement et à haut niveau d'abstraction. Ceci permet l'exploration du sous-système de mémoire grâce à la facilité de configuration de l'architecture du contrôleur de mémoire. En raison de la discontinuité de services entre le réseau sur puce et le contrôleur de mémoire, nous proposons également dans le cadre de cette thèse un protocole de contrôle de flux de bout en bout pour accéder à la mémoire à travers un contrôleur de mémoire multiports. L'idée, simple sur le principe mais novatrice car jamais proposée à notre connaissance, se base sur l'exploitation des informations sur l'état du contrôleur de mémoire dans le réseau intégré. Les résultats expérimentaux montrent qu'en contrôlant l'injection du trafic de service au mieux dans le réseau intégré, notre protocole augmente les performances du trafic de service garanti en termes de bande passante et de latence, tout en préservant la bande passante moyenne du trafic de service au mieux. / The ongoing advancements in VLSI technology allow System-on-Chip (SoC) to integrate many heterogeneous functions into a single chip, but still demand, because of economical constraints, a single and shared main off-chip SDRAM. Consequently, main memory system design, and more specifically the architecture of the memory controller, has become an increasingly important factor in determining the overall system performance. Choosing a memory controller design that meets the needs of the whole system is a complex issue. This requires the exploration of the memory controller architecture, and then the validation of each configuration by simulation. Although the architecture exploration of the memory controller is a key to successful system design, state of the art memory controllers are not as flexible as necessary for this task. Even if some of them present a configurable architecture, the exploration is restricted to limited sets of parameters such as queue depth, data bus size, quality-of-service level, and bandwidth distribution. Several classes of traffic co-exist in real applications, e.g. best effort traffic and guaranteed service traffic, and access the main memory. Therefore, considering the interaction between the memory subsystem and the interconnection system has become vital in today's SoCs. Many on chip networks provide guaranteed services to traffic classes to satisfy the applications requirements. However, very few studies consider the SDRAM access within a system approach, and take into account the specificity of the SDRAM access as a target in NoC-based SoCs. This thesis addresses the topic of dynamic access to SDRAM in NoC-based SoCs. We introduce a totally customizable memory controller architecture based on fully configurable building components and design a high level cycle approximate model for it. This enables the exploration of the memory subsystem thanks to the ease of configuration of the memory controller architecture. Because of the discontinuity of services between the network and the memory controller, we also propose within the framework of this thesis an Extreme End to End flow control protocol to access the memory device through a multi-port memory controller. The simple yet novel idea is to exploit information about the memory controller status in the NoC. Experimental results show that by controlling the best effort traffic injection in the NoC, our protocol increases the performance of the guaranteed service traffic in terms of bandwidth and latency, while maintaining the average bandwidth of the best effort traffic.

Time Sensitive Networking (TSN) defined in the IEEE 802.1 working group, is an important enabler for industrial Internet of things, specifically industry 4.0. 3GPP release 16 specifications includes the 5G system as a logical TSN bridge, thus promoting the integration of 5G technology with TSN. This combination provides wireless deterministic communication thus ensuring low, bounded delay and near-zero packet loss. In this thesis, we implement a 5G system in- tegration with TSN using a discrete event network simulator (NS-3). Further, we propose a simplified per egress port scheduling algorithm based on IEEE 802.1Q (scheduled traffic standard) running in the Centralized Network Con- troller (CNC). Average packet delay, average jitter, average throughput and the packet loss is measured for comparing the performance difference when our TSN scheduler is used versus when it is not. The designed system is tested by measuring it’s network impact in terms of average delay and packet loss. The 5GS logical bridge behavior is simulated by varying the 5G bridge de- lay dynamically. For every frame transmission in the queue, the processing delay of a particular bridge is varied with pre-defined set of values. Two sets of 5GS bridge delay variations are considered, i.e. between 1-10ms and 5- 10ms respectively. On calculating the network impact, we conclude that the overall impact on the network decreases as the variation range for the delay gets smaller. This proves that higher delay variations have a significant impact whereas smaller delay variations have a negligible impact on the network. For the latter case, the system delay is considerably stable and thus can be used for industrial applications in real-life TSN scenarios. / Tidskritiska nätverk (TSN) definierat i IEEE 802.1-arbetsgruppen, är en vik- tig faktor för det industriella Sakernas Internet, särskilt när det gäller Industri4.0. Specifikationer enligt 3GPP release 16 inkluderar 5G-system som en lo- gisk TSN-brygga, som främjar integrationen av 5G-teknik med TSN. 5G med TSN ger trådlös deterministisk kommunikation som säkerställer låg, begrän- sad fördröjning och nästan noll paketförlust. I denna rapport implementerar vi en 5G-systemintegration med TSN med hjälp av en diskret händelse simu- lator (NS-3). Dessutom föreslår vi en förenklad algoritm för schemaläggning av portar per utgång baserat på IEEE 802.1Q (Scheduled Traffic Standard) som körs i en centraliserad nätverks-controller (CNC). Genomsnittlig paket- fördröjning, genomsnittlig fördröjningsvariation, genomsnittlig genomström- ning och paketförlust mäts för att jämföra prestandaskillnaden när vår TSN- schemaläggare används jämfört med när den inte används. Det utformade sy- stemet testas genom att mäta nätverkets påverkan i termer av genomsnittlig fördröjning och paketförlust. 5GS logiska bryggbeteende simuleras genom att dynamiskt variera 5G-bryggfördröjningen. För varje bildöverföring varieras bryggans bearbetningsfördröjning med en fördefinierad uppsättning värden. Två fördefinierade uppsättningar av 5GS-fördröjningsvariationer beaktas som ligger mellan 1-10ms respektive 5-10ms. När vi beräknar nätverkspåverkan drar vi slutsatsen att den totala effekten på nätverket minskar när variationen i fördröjningen blir mindre. Detta visar att högre fördröjningsvariationer har en signifikant effekt medan mindre fördröjningsvariationer har en försumbar effekt. I det senare fallet är systemfördröjningen betydligt stabilare och kan användas för tillämpningar i verkliga TSN-scenarier.